| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 158 SDValue JoinIntegers(SDValue Lo, SDValue Hi);
170 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
172 SDValue &Lo, SDValue &Hi);
296 /// of Op are exactly equal to the bits of Lo; the high bits exactly equal Hi.
298 /// method returns the two i32's, with Lo being equal to the lower 32 bits of
300 void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
301 void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
306 SDValue &Lo, SDValue &Hi);
307 void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
308 void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi)
[all...] |
| LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part
31 // These routines assume that the Lo/Hi part is stored first in memory on
32 // little/big-endian machines, followed by the Hi/Lo part. This means that
33 // they cannot be used as is on vectors, for which Lo is always stored first.
35 SDValue &Lo, SDValue &Hi) {
37 GetExpandedOp(Op, Lo, Hi);
40 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
56 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 239 SDValue Lo, Hi;
240 GetSplitVector(N->getOperand(0), Lo, Hi);
241 Lo = BitConvertToInteger(Lo);
245 std::swap(Lo, Hi);
250 JoinIntegers(Lo, Hi));
[all...] |
| LegalizeVectorTypes.cpp | 407 SDValue Lo, Hi;
418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
420 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
421 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
422 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
427 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break
[all...] |
| LegalizeTypes.cpp | 764 void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo,
770 Lo = Entry.first;
774 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
776 assert(Lo.getValueType() ==
778 Hi.getValueType() == Lo.getValueType() &&
780 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
781 AnalyzeNewValue(Lo);
787 Entry.first = Lo;
791 void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo,
797 Lo = Entry.first
[all...] |
| LegalizeDAG.cpp | 475 SDValue Lo = Val;
480 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
486 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
597 SDValue Lo, Hi;
599 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
614 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
624 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
626 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
[all...] |
| /external/llvm/include/llvm/Support/ |
| SwapByteOrder.h | 34 uint16_t Lo = value >> 8;
35 return Hi | Lo;
66 uint32_t Lo = SwapByteOrder_32(uint32_t(value >> 32));
67 return (Hi << 32) | Lo;
|
| GCOV.h | 136 uint64_t Lo = readInt();
138 uint64_t Result = Lo | (Hi << 32);
|
| MathExtras.h | 209 // leading zeros in hi portion plus all bits in lo portion
212 // get lo portion
213 uint32_t Lo = Lo_32(Value);
215 Count = CountLeadingZeros_32(Lo)+32;
|
| /external/llvm/lib/Target/Mips/ |
| MipsJITInfo.cpp | 127 // addiu $t9, $t9, %lo(NewVal)
134 int Lo = (int)(NewVal & 0xffff);
137 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo;
174 int Lo = (int)(EmittedAddr & 0xffff);
177 // addiu t9, t9, %lo(EmittedAddr)
181 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
|
| MipsISelDAGToDAG.cpp | 164 // addiu $2, $2, %lo($CPI1_0)
168 // lwc1 $f0, %lo($CPI1_0)($2)
171 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
254 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
256 InFlag = SDValue(Lo,1);
260 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
|
| MipsISelLowering.cpp | 54 case MipsISD::Lo: return "MipsISD::Lo";
247 // multHi/Lo: product of multiplication
248 // Lo0: initial value of Lo register
301 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
321 // multHi/Lo: product of multiplication
322 // Lo0: initial value of Lo register
375 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
422 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
[all...] |
| MipsISelLowering.h | 37 // No relation with Mips Lo register
38 Lo,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
124 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
125 Addr.getOperand(1).getOpcode() == SPISD::Lo)
|
| SparcISelLowering.h | 32 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| SparcISelLowering.cpp | 475 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
483 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
490 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
506 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
704 // Custom legalize GlobalAddress nodes into LO/HI parts.
[all...] |
| /frameworks/media/libvideoeditor/vss/3gpwriter/inc/ |
| M4MP4W_Utils.h | 96 * Put Hi and Lo u16 part in a u32 variable
100 M4OSA_Void M4MP4W_put32_Lo(M4OSA_UInt32* tab, M4OSA_UInt16 Lo);
|
| /external/clang/lib/CodeGen/ |
| TargetInfo.cpp | 849 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
855 /// \param Lo - The classification for the parts of the type
861 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
866 /// \param Lo - The classification for the parts of the type
877 /// be passed in Memory then at least the classification of \arg Lo
880 /// The \arg Lo class will be NoClass iff the argument is ignored.
882 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
884 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi) const;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| AsmPrinter.h | 331 /// EmitLabelDifference - Emit something like ".long Hi-Lo" where the size
332 /// in bytes of the directive is specified by Size and Hi/Lo specify the
334 void EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo,
337 /// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo"
338 /// where the size in bytes of the directive is specified by Size and Hi/Lo
341 const MCSymbol *Lo, unsigned Size) const;
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DIE.h | 341 DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo)
342 : DIEValue(isDelta), LabelHi(Hi), LabelLo(Lo) {}
|
| /frameworks/media/libvideoeditor/vss/3gpwriter/src/ |
| M4MP4W_Utils.c | 289 M4OSA_Void M4MP4W_put32_Lo(M4OSA_UInt32* tab, M4OSA_UInt16 Lo)
293 *tab |= Lo;
|
| /external/skia/src/core/ |
| SkMath.cpp | 109 uint32_t lo = C + (B << 16); local
110 int32_t hi = A + (B >> 16) + (lo < C);
113 hi = -hi - Sk32ToBool(lo);
114 lo = 0 - lo;
119 SkASSERT(((int32_t)lo >> 31) == hi);
121 return lo;
129 // we want (hi << (32 - shift)) | (lo >> shift) but rounded
130 int roundBit = (lo >> (shift - 1)) & 1;
131 return ((hi << (32 - shift)) | (lo >> shift)) + roundBit
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 563 SDValue Lo(Hi.getNode(), 1);
564 SDValue Ops[] = { Lo, Hi };
580 SDValue Lo(Hi.getNode(), 1);
581 SDValue Ops[] = { Lo, Hi };
677 SDValue Lo(Hi.getNode(), 1);
678 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
685 SDValue Lo(Hi.getNode(), 1);
686 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
696 SDValue Lo(Hi.getNode(), 1);
701 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 32 Lo, ///< Low address component (lower 16)
|
