/external/llvm/lib/CodeGen/ |
RegAllocBase.h | 85 LiveIntervalUnion& operator[](unsigned PhysReg) { 86 assert(PhysReg < NumRegs && "physReg out of bounds"); 87 return Array[PhysReg]; 98 // Current queries, one per physreg. They must be reinitialized each time we 113 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) { 114 Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]); 115 return Queries[PhysReg]; 140 // Each call must guarantee forward progess by returning an available PhysReg [all...] |
RegisterClassInfo.h | 102 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR. 103 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { 104 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 105 if (unsigned N = CSRNum[PhysReg]) 110 /// isReserved - Returns true when PhysReg is a reserved register. 115 bool isReserved(unsigned PhysReg) const { 116 return Reserved.test(PhysReg); 119 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 125 bool isAllocatable(unsigned PhysReg) const { 126 return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg) [all...] |
AllocationOrder.h | 67 /// isHint - Return true if PhysReg is a preferred register. 68 bool isHint(unsigned PhysReg) const { return PhysReg == Hint; }
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RegAllocFast.cpp | 74 unsigned PhysReg; // Currently held here. 78 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0), 160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 161 unsigned calcSpillCost(unsigned PhysReg) const; 162 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg); 169 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg); 216 if (MO.getReg() == LR.PhysReg) 219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); 227 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping"); 228 PhysRegState[LR.PhysReg] = regFree [all...] |
InterferenceCache.h | 37 /// of PhysReg in all basic blocks. 39 /// PhysReg - The register currently represented. 40 unsigned PhysReg; 59 /// PhysReg. 74 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0) {} 78 PhysReg = 0; 83 unsigned getPhysReg() const { return PhysReg; } 91 /// valid - Return true if this is a valid entry for physReg. 94 /// reset - Initialize entry to represent physReg's aliases. 95 void reset(unsigned physReg, [all...] |
RegAllocBasic.cpp | 189 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { 190 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI)); 191 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg]; 192 PhysReg2LiveUnion[PhysReg].verify(VRegs); 205 unsigned PhysReg = VRM->getPhys(reg); 206 if (!unionVRegs[PhysReg].test(reg)) { 208 TRI->getName(PhysReg) << "\n"; 276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) { [all...] |
VirtRegRewriter.cpp | 169 // indicating which stack slot values are currently held by a physreg. This 171 // physreg is modified. 174 void disallowClobberPhysRegOnly(unsigned PhysReg); 176 void ClobberPhysRegOnly(unsigned PhysReg); 191 /// available in a physical register, return that PhysReg, otherwise 203 /// in the specified physreg. If CanClobber is true, the physreg can be 206 // If this stack slot is thought to be available in some other physreg, 219 DEBUG(dbgs() << " in physreg " << TRI->getName(Reg) 225 /// specified stack slot must be available in a physreg for this query t [all...] |
RegisterClassInfo.cpp | 86 unsigned PhysReg = RawOrder[i]; 88 if (Reserved.test(PhysReg)) 90 if (CSRNum[PhysReg]) 91 // PhysReg aliases a CSR, save it for later. 92 CSRAlias.push_back(PhysReg); 94 RCI.Order[N++] = PhysReg;
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RegAllocGreedy.cpp | 184 unsigned PhysReg; 189 // Interference for PhysReg. 197 PhysReg = Reg; 217 /// Candidate info for for each PhysReg in AllocationOrder. 359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { 360 unassign(LIS->getInterval(VirtReg), PhysReg); 369 unsigned PhysReg = VRM->getPhys(VirtReg); 370 if (!PhysReg) 375 unassign(LI, PhysReg); 448 unsigned PhysReg; [all...] |
InterferenceCache.cpp | 36 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { 37 unsigned E = PhysRegEntries[PhysReg]; 38 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { 54 Entries[E].reset(PhysReg, LIUArray, TRI, MF); 55 PhysRegEntries[PhysReg] = E; 71 void InterferenceCache::Entry::reset(unsigned physReg, 78 PhysReg = physReg; 81 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS) { 97 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS, ++i) [all...] |
VirtRegMap.cpp | 120 unsigned physReg = Hint.second; 121 if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg)) 122 physReg = getPhys(physReg); 124 return (TargetRegisterInfo::isPhysicalRegister(physReg)) 125 ? physReg : 0; 126 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF); 282 unsigned PhysReg = getPhys(VirtReg); 283 assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg") [all...] |
VirtRegMap.h | 184 void assignVirt2Phys(unsigned virtReg, unsigned physReg) { 186 TargetRegisterInfo::isPhysicalRegister(physReg)); 190 Virt2PhysMap[virtReg] = physReg; 211 /// @brief returns true if VirtReg is assigned to its preferred physreg. 389 void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) { 391 EmergencySpillMap[MI].push_back(PhysReg); 394 PhysRegs.push_back(PhysReg);
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LiveIntervalAnalysis.cpp | 201 unsigned PhysReg = mop.getReg(); 202 if (PhysReg == 0 || PhysReg == li.reg) 204 if (TargetRegisterInfo::isVirtualRegister(PhysReg)) { 205 if (!vrm.hasPhys(PhysReg)) 207 PhysReg = vrm.getPhys(PhysReg); 209 if (PhysReg && tri_->regsOverlap(PhysReg, reg)) 236 unsigned PhysReg = MO.getReg() [all...] |
RegAllocLinearScan.cpp | 313 void addRegUse(unsigned physReg) { 314 assert(TargetRegisterInfo::isPhysicalRegister(physReg) && 316 ++regUse_[physReg]; 317 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) 321 void delRegUse(unsigned physReg) { 322 assert(TargetRegisterInfo::isPhysicalRegister(physReg) && 324 assert(regUse_[physReg] != 0); 325 --regUse_[physReg]; 326 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) { 332 bool isRegAvail(unsigned physReg) const [all...] |
/external/llvm/utils/TableGen/ |
FastISelEmitter.cpp | 399 std::string PhysReg; 402 return PhysReg; 407 return PhysReg; 409 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \ 411 PhysReg += "::"; 412 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); 413 return PhysReg; 515 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); 516 if (PhysReg.empty()) { 526 PhysRegInputs->push_back(PhysReg); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.cpp | 105 unsigned &PhysReg, int &Cost) { 118 PhysReg = Reg; 428 unsigned PhysReg = 0; 431 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 432 assert((PhysReg == 0 || !isChain) && 433 "Chain dependence via physreg data?"); 440 PhysReg = 0; 449 OpLatency, PhysReg);
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SelectionDAGBuilder.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
LiveIntervalAnalysis.h | 286 unsigned PhysReg, VirtRegMap &vrm); 307 unsigned PhysReg) const;
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