/external/libvpx/build/make/ |
ads2gas.pl | 41 # Convert :SHL: to << 42 s/:SHL:/ << /g;
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ads2gas_apple.pl | 59 # Convert :SHL: to << 60 s/:SHL:/ << /g;
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/external/llvm/lib/Target/ARM/ |
ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl;
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/dalvik/dexgen/src/com/android/dexgen/rop/code/ |
RegOps.java | 115 public static final int SHL = 23; 336 case SHL: return "shl";
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DexTranslationAdvice.java | 81 case RegOps.SHL:
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Rops.java | 339 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT_INT, "shl-int"); 343 new Rop(RegOps.SHL, Type.LONG, StdTypeList.LONG_INT, "shl-long"); 484 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT, "shl-const-int"); 488 new Rop(RegOps.SHL, Type.LONG, StdTypeList.INT, "shl-const-long"); [all...] |
/dalvik/dx/src/com/android/dx/rop/code/ |
RegOps.java | 115 public static final int SHL = 23; 336 case SHL: return "shl";
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DexTranslationAdvice.java | 88 case RegOps.SHL:
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Rops.java | 339 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT_INT, "shl-int"); 343 new Rop(RegOps.SHL, Type.LONG, StdTypeList.LONG_INT, "shl-long"); 484 new Rop(RegOps.SHL, Type.INT, StdTypeList.INT, "shl-const-int"); 488 new Rop(RegOps.SHL, Type.LONG, StdTypeList.INT, "shl-const-long"); [all...] |
/external/v8/src/ |
token.h | 98 T(SHL, "<<", 11) \ 261 return (SHL <= op) && (op <= SHR);
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builtins.h | 224 V(SHL, 1) \
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/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 346 if (Opcode == ISD::SHL) { 397 if (Op0.getOperand(0).getOpcode() == ISD::SHL || 399 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 406 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 407 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 419 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 422 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 426 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 429 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; [all...] |
PPCISelLowering.h | 91 SRL, SRA, SHL,
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/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR, 375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL
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MSP430ISelLowering.cpp | 99 setOperationAction(ISD::SHL, MVT::i8, Custom); 102 setOperationAction(ISD::SHL, MVT::i16, Custom); 182 case ISD::SHL: // FALLTHROUGH 604 case ISD::SHL: 605 return DAG.getNode(MSP430ISD::SHL, dl, 630 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 70 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 528 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 717 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, [all...] |
DAGCombiner.cpp | [all...] |
LegalizeDAG.cpp | 623 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); [all...] |
TargetLowering.cpp | [all...] |
/external/openssl/crypto/sha/asm/ |
sha512-ppc.pl | 45 $SHL="sldi"; 52 $SHL="slwi"; 184 $SHL $num,$num,`log(16*$SZ)/log(2)`
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/external/speex/libspeex/ |
arch.h | 178 #define SHL(a,shift) (a)
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fixed_generic.h | 60 #define SHL(a,shift) ((spx_word32_t)(a) << (shift))
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/dalvik/dx/src/com/android/dx/ssa/ |
SCCP.java | 437 case RegOps.SHL: 516 case RegOps.SHL:
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/external/v8/src/ia32/ |
code-stubs-ia32.cc | 527 case Token::SHL: 566 case Token::SHL: 697 case Token::SHL: 712 case Token::SHL: 740 case Token::SHL: { 830 case Token::SHL: 865 case Token::SHL: 892 case Token::SHL: [all...] |