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Searched
refs:ShiftOp
(Results
1 - 9
of
9
) sorted by null
/external/llvm/lib/Transforms/InstCombine/
InstCombineShifts.cpp
526
BinaryOperator *
ShiftOp
= dyn_cast<BinaryOperator>(Op0);
527
if (
ShiftOp
&& !
ShiftOp
->isShift())
528
ShiftOp
= 0;
530
if (
ShiftOp
&& isa<ConstantInt>(
ShiftOp
->getOperand(1))) {
531
ConstantInt *ShiftAmt1C = cast<ConstantInt>(
ShiftOp
->getOperand(1));
536
Value *X =
ShiftOp
->getOperand(0);
543
if (I.getOpcode() ==
ShiftOp
->getOpcode()) {
559
ShiftOp
->getOpcode() != Instruction::Shl)
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all
...]
/external/v8/src/arm/
constants-arm.h
287
enum
ShiftOp
{
294
// Use a special code to make the distinction. The RRX
ShiftOp
is only used
644
inline int ShiftValue() const { return static_cast<
ShiftOp
>(Bits(6, 5)); }
645
inline
ShiftOp
ShiftField() const {
646
return static_cast<
ShiftOp
>(BitField(6, 5));
assembler-arm.h
387
explicit Operand(Register rm,
ShiftOp
shift_op, int shift_imm);
390
explicit Operand(Register rm,
ShiftOp
shift_op, Register rs);
410
ShiftOp
shift_op() const { return shift_op_; }
415
ShiftOp
shift_op_;
443
ShiftOp
shift_op, int shift_imm, AddrMode am = Offset);
466
ShiftOp
shift_op_;
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...]
disasm-arm.cc
211
ShiftOp
shift = instr->ShiftField();
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...]
assembler-arm.cc
168
Operand::Operand(Register rm,
ShiftOp
shift_op, int shift_imm) {
184
Operand::Operand(Register rm,
ShiftOp
shift_op, Register rs) {
210
ShiftOp
shift_op, int shift_imm, AddrMode am) {
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...]
simulator-arm.cc
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...]
/external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp
566
unsigned
ShiftOp
= MI->getOperand(OpNum).getImm();
567
bool isASR = (
ShiftOp
& (1 << 5)) != 0;
568
unsigned Amt =
ShiftOp
& 0x1f;
/external/llvm/lib/Target/ARM/
ARMCodeEmitter.cpp
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...]
/external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp
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...]
Completed in 1230 milliseconds