| /external/llvm/lib/CodeGen/ |
| PHIEliminationUtils.h | 17 /// SrcReg when following the CFG edge to SuccMBB. This needs to be after
18 /// any def of SrcReg, but before any subsequent point where control flow
22 unsigned SrcReg);
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| RegisterCoalescer.h | 36 /// SrcReg - the virtual register that will be coalesced into dstReg.
37 unsigned SrcReg;
39 /// subReg_ - The subregister index of srcReg in DstReg. It is possible the
40 /// coalesce SrcReg into a subreg of the larger DstReg when DstReg is a
50 /// Flipped - True when DstReg and SrcReg are reversed from the oriignal
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
67 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
95 unsigned getSrcReg() const { return SrcReg; }
97 /// getSubIdx - Return the subregister index in DstReg that SrcReg will be
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| PHIEliminationUtils.cpp | 17 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
19 // SrcReg, but before any subsequent point where control flow might jump out of
23 unsigned SrcReg) {
37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg),
|
| PHIElimination.cpp | 175 unsigned SrcReg = MPhi->getOperand(i).getReg();
176 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
285 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
288 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
297 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
312 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
317 TII->get(TargetOpcode::COPY), IncomingReg).addReg(SrcReg, 0, SrcSubReg);
334 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
338 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
346 if (Term != opBlock.end() && Term->readsRegister(SrcReg)) {
[all...] |
| TwoAddressInstructionPass.cpp | 393 unsigned &SrcReg, unsigned &DstReg,
395 SrcReg = 0;
399 SrcReg = MI.getOperand(1).getReg();
402 SrcReg = MI.getOperand(2).getReg();
406 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
442 unsigned SrcReg, DstReg;
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
447 Reg = SrcReg;
484 unsigned SrcReg;
486 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| StrongPHIElimination.cpp | 250 unsigned SrcReg = SrcMO.getReg();
251 addReg(SrcReg);
252 unionRegs(DestReg, SrcReg);
254 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
292 unsigned SrcReg = BBI->getOperand(i).getReg();
293 addReg(SrcReg);
294 unionRegs(DestReg, SrcReg);
309 unsigned SrcReg = PHI->getOperand(1).getReg();
310 unsigned SrcColor = getRegColor(SrcReg);
313 NewReg = SrcReg;
[all...] |
| OptimizePHIs.cpp | 100 unsigned SrcReg = MI->getOperand(i).getReg();
101 if (SrcReg == DstReg)
103 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
121 SingleValReg = SrcReg;
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| /external/llvm/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 102 unsigned DestReg, unsigned SrcReg,
104 if (BF::ALLRegClass.contains(DestReg, SrcReg)) {
106 .addReg(SrcReg, getKillRegState(KillSrc));
110 if (BF::D16RegClass.contains(DestReg, SrcReg)) {
112 .addReg(SrcReg, getKillRegState(KillSrc))
118 if (SrcReg == BF::NCC) {
120 .addReg(SrcReg, getKillRegState(KillSrc));
124 if (SrcReg == BF::CC) {
126 .addReg(SrcReg, getKillRegState(KillSrc));
131 if (BF::DRegClass.contains(SrcReg)) {
[all...] |
| BlackfinInstrInfo.h | 51 unsigned DestReg, unsigned SrcReg,
56 unsigned SrcReg, bool isKill,
62 unsigned SrcReg, bool isKill,
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| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 37 unsigned DestReg, unsigned SrcReg,
40 .addReg(SrcReg, getKillRegState(KillSrc)));
41 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
47 unsigned SrcReg, bool isKill, int FI,
51 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
52 isARMLowRegister(SrcReg))) && "Unknown regclass!");
55 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
56 isARMLowRegister(SrcReg))) {
69 .addReg(SrcReg, getKillRegState(isKill))
|
| Thumb1InstrInfo.h | 42 unsigned DestReg, unsigned SrcReg,
46 unsigned SrcReg, bool isKill, int FrameIndex,
|
| Thumb2InstrInfo.h | 43 unsigned DestReg, unsigned SrcReg,
48 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 312 unsigned DestReg, unsigned SrcReg,
315 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
317 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
319 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
321 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
323 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
325 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
333 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
335 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| PPCInstrInfo.h | 72 unsigned SrcReg, bool isKill, int FrameIdx,
117 unsigned DestReg, unsigned SrcReg,
122 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.h | 42 unsigned DstReg, unsigned SrcReg,
47 unsigned DstReg, unsigned SrcReg,
53 unsigned &SrcReg, unsigned &DstReg,
104 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 104 unsigned DestReg, unsigned SrcReg,
109 if (Mips::CPURegsRegClass.contains(SrcReg))
111 else if (Mips::CCRRegClass.contains(SrcReg))
113 else if (Mips::FGR32RegClass.contains(SrcReg))
115 else if (SrcReg == Mips::HI)
116 Opc = Mips::MFHI, SrcReg = 0;
117 else if (SrcReg == Mips::LO)
118 Opc = Mips::MFLO, SrcReg = 0;
120 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
130 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
[all...] |
| MipsInstrInfo.h | 160 unsigned DestReg, unsigned SrcReg,
164 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaInstrInfo.h | 47 unsigned DestReg, unsigned SrcReg,
51 unsigned SrcReg, bool isKill, int FrameIndex,
|
| AlphaInstrInfo.cpp | 123 unsigned DestReg, unsigned SrcReg,
125 if (Alpha::GPRCRegClass.contains(DestReg, SrcReg)) {
127 .addReg(SrcReg)
128 .addReg(SrcReg, getKillRegState(KillSrc));
129 } else if (Alpha::F4RCRegClass.contains(DestReg, SrcReg)) {
131 .addReg(SrcReg)
132 .addReg(SrcReg, getKillRegState(KillSrc));
133 } else if (Alpha::F8RCRegClass.contains(DestReg, SrcReg)) {
135 .addReg(SrcReg)
136 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.h | 49 unsigned DestReg, unsigned SrcReg,
55 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 57 unsigned DestReg, unsigned SrcReg,
62 unsigned SrcReg, bool isKill,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 80 unsigned DestReg, unsigned SrcReg,
85 unsigned SrcReg, bool isKill, int FrameIndex,
|
| SparcInstrInfo.cpp | 271 unsigned DestReg, unsigned SrcReg,
273 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
275 .addReg(SrcReg, getKillRegState(KillSrc));
276 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
278 .addReg(SrcReg, getKillRegState(KillSrc));
279 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
281 .addReg(SrcReg, getKillRegState(KillSrc));
288 unsigned SrcReg, bool isKill, int FI,
294 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
297 .addReg(SrcReg, getKillRegState(isKill))
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 67 unsigned DestReg, unsigned SrcReg,
75 unsigned SrcReg, bool isKill,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 66 unsigned DestReg, unsigned SrcReg,
71 unsigned SrcReg, bool isKill, int FrameIndex,
|
