/external/llvm/lib/Target/ARM/ |
Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx)
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ARMBaseInstrInfo.h | 306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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MLxExpansionPass.cpp | 233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
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ARMLoadStoreOptimizer.cpp | 359 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 748 .addReg(Base, getDefRegState(true)) // WB base register 903 .addReg(Base, getDefRegState(true)) // WB base register 906 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : [all...] |
Thumb1FrameLowering.cpp | 377 MIB.addReg(Reg, getDefRegState(true));
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Thumb1RegisterInfo.cpp | 78 .addReg(DestReg, getDefRegState(true), SubIdx)
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ARMBaseRegisterInfo.cpp | 796 .addReg(DestReg, getDefRegState(true), SubIdx) [all...] |
ARMFrameLowering.cpp | 651 MIB.addReg(Regs[i], getDefRegState(true)); [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineInstrBuilder.h | 246 inline unsigned getDefRegState(bool B) {
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/external/llvm/lib/Target/X86/ |
X86FrameLowering.cpp | 166 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); [all...] |
X86InstrInfo.cpp | [all...] |