| /external/llvm/include/llvm/MC/ |
| MCInstrAnalysis.h | 32 return Info->get(Inst.getOpcode()).isBranch();
36 return Info->get(Inst.getOpcode()).isConditionalBranch();
40 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
44 return Info->get(Inst.getOpcode()).isIndirectBranch();
48 return Info->get(Inst.getOpcode()).isCall();
52 return Info->get(Inst.getOpcode()).isReturn();
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| FixedSizeInsn.java | 52 return getOpcode().getFormat().codeSize();
58 getOpcode().getFormat().writeTo(out, this);
70 return getOpcode().getFormat().listingString(this, noteIndices);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| FixedSizeInsn.java | 53 return getOpcode().getFormat().codeSize();
59 getOpcode().getFormat().writeTo(out, this);
71 return getOpcode().getFormat().listingString(this, noteIndices);
|
| /external/llvm/include/llvm/ |
| Operator.h | 40 /// getOpcode - Return the opcode for this Instruction or ConstantExpr.
42 unsigned getOpcode() const {
44 return I->getOpcode();
45 return cast<ConstantExpr>(this)->getOpcode();
48 /// getOpcode - If V is an Instruction or ConstantExpr, return its
51 static unsigned getOpcode(const Value *V) {
53 return I->getOpcode();
55 return CE->getOpcode();
107 return I->getOpcode() == Instruction::Add ||
108 I->getOpcode() == Instruction::Sub |
[all...] |
| Instruction.h | 81 /// getOpcode() returns a member of one of the enums like Instruction::Add.
82 unsigned getOpcode() const { return getValueID() - InstructionVal; }
84 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); }
85 bool isTerminator() const { return isTerminator(getOpcode()); }
86 bool isBinaryOp() const { return isBinaryOp(getOpcode()); }
87 bool isShift() { return isShift(getOpcode()); }
88 bool isCast() const { return isCast(getOpcode()); }
108 return getOpcode() == Shl || getOpcode() == LShr;
113 return getOpcode() == AShr
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
|
| MCInst.cpp | 39 OS << "<MCInst " << getOpcode();
50 OS << "<MCInst #" << getOpcode();
54 OS << ' ' << Printer->getOpcodeName(getOpcode());
|
| /external/llvm/lib/Target/PTX/ |
| PTXMCInstLower.cpp | 25 OutMI.setOpcode(MI->getOpcode());
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| NormalSsaInsn.java | 128 public Rop getOpcode() {
129 return insn.getOpcode();
143 if (insn.getOpcode().getOpcode() == RegOps.MARK_LOCAL) {
180 return insn.getOpcode().getOpcode() == RegOps.MOVE;
186 return insn.getOpcode().getOpcode() == RegOps.MOVE_EXCEPTION;
218 Rop opcode = getOpcode();
227 switch (opcode.getOpcode()) {
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 80 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
81 Addr.getOpcode() == ISD::TargetGlobalAddress)
84 if (Addr.getOpcode() == ISD::ADD) {
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
115 if (Addr.getOpcode() == ISD::FrameIndex) return false;
116 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
117 Addr.getOpcode() == ISD::TargetGlobalAddress)
120 if (Addr.getOpcode() == ISD::ADD) {
124 if (Addr.getOperand(0).getOpcode() == SPISD::Lo |
[all...] |
| FPMover.cpp | 90 if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
91 MI->getOpcode() == SP::FpNEGD) {
95 if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) {
106 if (MI->getOpcode() == SP::FpMOVD)
108 else if (MI->getOpcode() == SP::FpNEGD)
110 else if (MI->getOpcode() == SP::FpABSD)
|
| /dalvik/dx/src/com/android/dx/rop/code/ |
| PlainInsn.java | 92 return new PlainInsn(getOpcode(), getPosition(),
115 Rop newRop = Rops.ropFor(getOpcode().getOpcode(), getResult(),
130 int opcode = getOpcode().getOpcode();
152 return new PlainInsn(getOpcode(), getPosition(),
|
| ThrowingCstInsn.java | 84 return new ThrowingCstInsn(getOpcode(), getPosition(),
92 return new ThrowingCstInsn(getOpcode(), getPosition(),
103 return new ThrowingCstInsn(getOpcode(), getPosition(),
|
| ThrowingInsn.java | 99 return new ThrowingInsn(getOpcode(), getPosition(),
106 return new ThrowingInsn(getOpcode(), getPosition(),
116 return new ThrowingInsn(getOpcode(), getPosition(),
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaBranchSelector.cpp | 51 if (MBBI->getOpcode() == Alpha::COND_BRANCH_I ||
52 MBBI->getOpcode() == Alpha::COND_BRANCH_F) {
|
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| PlainInsn.java | 91 return new PlainInsn(getOpcode(), getPosition(),
118 newRop = Rops.ropFor(getOpcode().getOpcode(),
135 return new PlainInsn(getOpcode(), getPosition(),
|
| ThrowingCstInsn.java | 79 return new ThrowingCstInsn(getOpcode(), getPosition(),
87 return new ThrowingCstInsn(getOpcode(), getPosition(),
98 return new ThrowingCstInsn(getOpcode(), getPosition(),
|
| ThrowingInsn.java | 99 return new ThrowingInsn(getOpcode(), getPosition(),
106 return new ThrowingInsn(getOpcode(), getPosition(),
116 return new ThrowingInsn(getOpcode(), getPosition(),
|
| /dalvik/dx/src/com/android/dx/io/instructions/ |
| ZeroRegisterDecodedInstruction.java | 41 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 193 /// getOpcode - Returns the opcode of this MachineInstr.
195 int getOpcode() const { return MCID->Opcode; }
258 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
259 getOpcode() == TargetOpcode::EH_LABEL ||
260 getOpcode() == TargetOpcode::GC_LABEL;
264 return getOpcode() == TargetOpcode::PROLOG_LABEL;
266 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
267 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
268 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
270 bool isPHI() const { return getOpcode() == TargetOpcode::PHI;
[all...] |
| SelectionDAGNodes.h | 136 inline unsigned getOpcode() const;
354 /// getOpcode - Return the SelectionDAG opcode value for this node. For
358 unsigned getOpcode() const { return (unsigned short)NodeType; }
769 inline unsigned SDValue::getOpcode() const {
770 return Node->getOpcode();
956 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode();
122 if (N.getOpcode() == ISD::FrameIndex) return false;
123 if (N.getOpcode() == ISD::TargetExternalSymbol ||
124 N.getOpcode() == ISD::TargetGlobalAddress)
128 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
132 if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
133 N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
153 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
80 int Opcode = MI->getOpcode();
209 if (IsBRU(LastInst->getOpcode())) {
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
235 unsigned SecondLastOpc = SecondLastInst->getOpcode();
241 && IsBRU(LastInst->getOpcode())) {
253 if (IsBRU(SecondLastInst->getOpcode()) &&
254 IsBRU(LastInst->getOpcode())) {
263 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 371 if (Op.getOpcode() == ISD::FNEG) return 2;
379 switch (Op.getOpcode()) {
423 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
429 switch (Op.getOpcode()) {
470 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
476 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
483 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
502 if (N.getOpcode() == ISD::SETCC) {
508 if (N.getOpcode() == ISD::SELECT_CC &&
509 N.getOperand(2).getOpcode() == ISD::Constant &
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 106 switch (I->getOpcode()) {
200 switch (I->getOpcode()) {
313 bool isLeftShift = I.getOpcode() == Instruction::Shl;
318 if (I.getOpcode() != Instruction::AShr &&
336 if (I.getOpcode() != Instruction::AShr)
345 if (BO->getOpcode() == Instruction::Mul && isLeftShift)
371 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
385 if (I.getOpcode() == Instruction::Shl)
388 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift");
407 switch (Op0BO->getOpcode()) {
[all...] |
