| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
152 const MachineOperand &Base = MI->getOperand(2);
155 unsigned BaseReg = Base.getReg();
[all...] |
| ARMFastISel.cpp | 71 } Base;
78 Base.Reg = 0;
793 // Try to grab the base operand now.
809 Addr.Base.FI = SI->second;
822 Addr.Base.Reg = Tmp;
827 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
828 return Addr.Base.Reg != 0;
854 // put the alloca address into a register, set the base type back to
[all...] |
| ARMISelDAGToDAG.cpp | 114 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
115 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
117 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
119 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
124 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
126 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
129 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
131 SelectAddrMode2Worker(N, Base, Offset, Opc);
132 // return SelectAddrMode2ShOp(N, Base, Offset, Opc)
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| ARMLoadStoreOptimizer.cpp | 91 int Offset, unsigned Base, bool BaseKill, int Opcode,
100 unsigned Base,
108 void MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
285 /// MergeOps - Create and insert a LDM or STM with Base as base register and
291 int Offset, unsigned Base, bool BaseKill,
309 // VLDM/VSTM do not support DB mode without also updating the base reg.
313 // calculate a new base register.
316 // If starting offset isn't zero, insert a MI to materialize a new base.
325 // use as the new base
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| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 545 SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP,
550 SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
553 DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 548 // After parsing the base expression we could either have a parenthesized
575 // After parsing the base expression we could either have a parenthesized
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| /external/llvm/unittests/ExecutionEngine/JIT/ |
| JITTest.cpp | 61 const OwningPtr<JITMemoryManager> Base;
64 : Base(JITMemoryManager::CreateDefaultMemManager()) {
68 virtual void setMemoryWritable() { Base->setMemoryWritable(); }
69 virtual void setMemoryExecutable() { Base->setMemoryExecutable(); }
70 virtual void setPoisonMemory(bool poison) { Base->setPoisonMemory(poison); }
71 virtual void AllocateGOT() { Base->AllocateGOT(); }
72 virtual uint8_t *getGOTBase() const { return Base->getGOTBase(); }
88 uint8_t *Result = Base->startFunctionBody(F, ActualSize);
97 return Base->allocateStub(F, StubSize, Alignment);
114 Base->endFunctionBody(F, FunctionStart, FunctionEnd)
[all...] |
| /external/llvm/utils/TableGen/ |
| FixedLenDecoderEmitter.cpp | 748 << "(insn, " << OI->Base << ", " << OI->Width
755 << "(insn, " << OI->Base << ", " << OI->Width
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| /external/chromium/testing/gmock/test/ |
| gmock-matchers_test.cc | 544 class Base {};
545 class Derived : public Base {};
569 // are pointers or references to a derived and a base class, correspondingly.
572 Matcher<Base*> m1 = Eq(&d);
577 Matcher<Base&> m3 = Ref(d);
966 // used wherever Ref(base) can be used (Ref(derived) is a sub-type
967 // of Ref(base), but not vice versa.
970 Base base, base2; local
972 Matcher<const Base&> m1 = Ref(base)
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| /external/clang/include/clang/AST/ |
| ExprCXX.h | 873 /// a base class (rather than a complete object)
[all...] |
| /external/clang/lib/AST/ |
| VTableBuilder.cpp | 29 /// indirect base class.
34 /// VirtualBase - If the path from the derived class to the base class
35 /// involves a virtual base class, this holds its declaration.
38 /// NonVirtualOffset - The offset from the derived class to the base class.
39 /// (Or the offset from the virtual base class to the base class, if the
40 /// path from the derived class to the base class involves a virtual base
55 /// member functions in the base subobjects of a class.
63 /// Offset - the base offset of the overrider in the layout class
[all...] |
| ExprConstant.cpp | 107 const Expr *Base;
110 const Expr *getLValueBase() { return Base; }
114 v = APValue(Base, Offset);
118 Base = v.getLValueBase();
155 const Expr* Base = Value.Base;
157 // A null base expression indicates a null pointer. These are always
159 if (!Base) {
164 // Require the base expression to be a global l-value.
165 if (!IsGlobalLValue(Base)) return false
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | 379 Value *Base = EmitScalarExpr(E->getArg(0));
381 llvm::Type *ArgType = Base->getType();
383 return RValue::get(Builder.CreateCall2(F, Base, Exponent));
[all...] |
| CGClass.cpp | 35 const CXXBaseSpecifier *Base = *I;
36 assert(!Base->isVirtual() && "Should not see virtual bases here!");
42 cast<CXXRecordDecl>(Base->getType()->getAs<RecordType>()->getDecl());
57 assert(PathBegin != PathEnd && "Base path should not be empty!");
71 /// Gets the address of a direct base class within a complete object.
79 const CXXRecordDecl *Base,
86 // Compute the offset of the virtual base.
90 Offset = Layout.getVBaseClassOffset(Base);
92 Offset = Layout.getBaseClassOffset(Base);
94 // Shift and cast down to the base type
[all...] |
| CGDebugInfo.cpp | 857 /// C++ base classes. This is used while creating debug info entry for
[all...] |
| CGExpr.cpp | 380 // Check if need to perform derived-to-base casts and/or field accesses, to
[all...] |
| CGObjC.cpp | [all...] |
| /external/clang/lib/Serialization/ |
| ASTReaderStmt.cpp | 87 #define STMT(Type, Base) \
450 case Node::Base: {
451 CXXBaseSpecifier *Base = new (Reader.getContext()) CXXBaseSpecifier();
452 *Base = Reader.ReadCXXBaseSpecifier(F, Record, Idx);
453 E->setComponent(I, Node(Base));
[all...] |
| /external/clang/test/SemaCXX/ |
| warn-thread-safety-analysis.cpp | 1102 class Base {
1109 class Child : public Base {
1117 Base *b = c;
1365 class Base {
1372 class Child : public Base {
1380 Base *b = c;
[all...] |
| type-traits.cpp | [all...] |
| /external/gtest/test/ |
| gtest_unittest.cc | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 231 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
385 AM.Base.FrameIndex = SI->second;
464 // addressing. Update the address state and move on to examining the base.
504 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
511 // If this reference is relative to the pic base, set it now.
513 // FIXME: How do we know Base.Reg is free??
514 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
522 // base and index registers are unused.
523 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
524 AM.Base.Reg = X86::RIP
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 289 SDValue base = getGlobalAddressWrapper(GA, GV, DAG); local
294 return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
366 const SDValue &Base = Addr.getOperand(0);
367 const SDValue *Root = &Base;
368 if (Base.getOpcode() == ISD::ADD &&
369 Base.getOperand(1).getOpcode() == ISD::SHL) {
370 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Base.getOperand(1)
373 Root = &Base.getOperand(0);
378 AlignedBase = Base;
385 AlignedBase = Base;
[all...] |
| /external/clang/lib/Sema/ |
| SemaType.cpp | [all...] |
