| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 22 #include "llvm/ADT/BitVector.h"
93 BitVector SubClasses;
161 // getSubClasses - Returns a constant BitVector of subclasses indexed by
164 const BitVector &getSubClasses() const { return SubClasses; }
|
| /sdk/emulator/qtools/ |
| q2g.cpp | 10 #include "bitvector.h"
|
| stack_dump.cpp | 9 #include "bitvector.h"
|
| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.h | 21 #include "llvm/ADT/BitVector.h"
58 BitVector Reserved;
|
| VirtRegRewriter.cpp | 272 void AddAvailableRegsToLiveIn(MachineBasicBlock &MBB, BitVector &RegKills,
382 BitVector PhysRegsClobbered;
422 BitVector &RegKills,
440 BitVector &RegKills,
474 BitVector &RegKills,
519 const TargetRegisterInfo* TRI, BitVector &RegKills,
543 BitVector &RegKills,
627 BitVector &RegKills,
780 BitVector &RegKills,
[all...] |
| StackSlotColoring.cpp | 31 #include "llvm/ADT/BitVector.h"
84 BitVector AllColors;
90 BitVector UsedColors;
132 BitVector &SlotIsReg);
256 BitVector &SlotIsReg) {
375 BitVector SlotIsReg(NumObjs);
376 BitVector UsedColors(NumObjs);
|
| AggressiveAntiDepBreaker.cpp | 129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
188 BitVector Pristine = MFI->getPristineRegs(BB);
514 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
515 BitVector BV(TRI->getNumRegs(), false);
532 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
565 // collect the BitVector of registers that can be used to rename
569 std::map<unsigned, BitVector> RenameRegisterMap;
580 BitVector BV = GetRenameRegisters(Reg);
581 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
666 BitVector BV = RenameRegisterMap[Reg]
[all...] |
| DeadMachineInstructionElim.cpp | 35 BitVector LivePhysRegs;
92 BitVector ReservedRegs = TRI->getReservedRegs(MF);
|
| VirtRegMap.cpp | 35 #include "llvm/ADT/BitVector.h"
231 BitVector Used(NumRegs);
238 BitVector Allocatable = TRI->getAllocatableSet(*MF);
|
| RegisterClassInfo.cpp | 57 BitVector RR = TRI->getReservedRegs(*MF);
|
| VirtRegMap.h | 23 #include "llvm/ADT/BitVector.h"
58 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs;
133 BitVector ImplicitDefed;
136 BitVector UnusedRegs;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 26 #include "llvm/ADT/BitVector.h"
77 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
78 BitVector Reserved(getNumRegs());
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 29 #include "llvm/ADT/BitVector.h"
86 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
87 BitVector Reserved(getNumRegs());
|
| /external/clang/lib/Analysis/ |
| CFGReachabilityAnalysis.cpp | 44 llvm::BitVector visited(analyzed.size());
|
| UninitializedValues.cpp | 285 llvm::BitVector enqueuedBlocks;
619 llvm::BitVector &wasAnalyzed,
700 llvm::BitVector previouslyVisited(cfg.getNumBlockIDs());
702 llvm::BitVector wasAnalyzed(cfg.getNumBlockIDs(), false);
|
| /external/llvm/unittests/ADT/ |
| PackedVectorTest.cpp | 11 // as well since it depends on a BitVector.
|
| SCCIteratorTest.cpp | 34 typedef unsigned char BitVector; // Where the limitation N <= 8 comes from.
35 BitVector Elements;
36 NodeSubset(BitVector e) : Elements(e) {}
40 assert(N <= sizeof(BitVector)*CHAR_BIT && "Graph too big!");
|
| /external/llvm/include/llvm/CodeGen/ |
| GCMetadata.h | 95 // FIXME: Liveness. A 2D BitVector, perhaps?
97 // BitVector Liveness;
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinRegisterInfo.cpp | 29 #include "llvm/ADT/BitVector.h"
52 BitVector
57 BitVector Reserved(getNumRegs());
|
| /external/v8/src/ |
| lithium-allocator.cc | 562 BitVector* LAllocator::ComputeLiveOut(HBasicBlock* block) {
565 BitVector* live_out = new BitVector(next_virtual_register_);
572 BitVector* live_in = live_in_sets_[successor->block_id()];
597 BitVector* live_out) {
604 BitVector::Iterator iterator(live_out);
892 void LAllocator::ProcessInstructions(HBasicBlock* block, BitVector* live) {
[all...] |
| hydrogen-instructions.cc | [all...] |
| /dalvik/vm/compiler/codegen/x86/ |
| X86LIR.h | 76 BitVector *nullCheckedRegs; // Track which registers have been null-checked
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 99 BitVector getReservedRegs(const MachineFunction &MF) const;
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.h | 67 BitVector getReservedRegs(const MachineFunction &MF) const;
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 104 BitVector getReservedRegs(const MachineFunction &MF) const;
|
