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  /dalvik/dx/src/com/android/dx/io/
IndexType.java 50 /** direct field offset (for static linked field accesses) */
  /dalvik/vm/compiler/
Loop.h 26 GrowableList *arrayAccessInfo; // hoisted checks for array accesses
  /external/clang/test/CodeGen/
arm-vaarg-align.c 4 * Check that va_arg accesses stack according to ABI alignment
  /external/javassist/src/main/javassist/tools/reflect/
package.html 8 accesses on a regular Java object. It provides a class
  /external/llvm/test/CodeGen/X86/
vec_ins_extract-1.ll 4 ; to memory accesses.
  /external/valgrind/main/drd/
drd.h 88 * Tell DRD to trace all memory accesses on the specified variable.
114 * Tell DRD that the memory accesses executed after this annotation will
115 * happen after all memory accesses performed before all preceding
279 * accesses that occurred before the corresponding ANNOTATE_PCQ_PUT(pcq)
280 * annotation and the memory accesses after this annotation. Correspondence
321 /** Tell DRD to ignore all memory accesses performed by the current thread. */
326 * Tell DRD to no longer ignore the memory accesses performed by the current
360 /* Ask the DRD tool to discard all information about memory accesses */
382 /* To ask the DRD tool to trace all accesses to the specified range. */
385 /* To ask the DRD tool to stop tracing accesses to the specified range. *
    [all...]
drd_segment.h 56 * Bitmap representing the memory accesses by the instructions associated
  /external/kernel-headers/original/asm-generic/bitops/
non-atomic.h 58 * but actually fail. You must protect multiple accesses with a lock.
77 * but actually fail. You must protect multiple accesses with a lock.
  /external/kernel-headers/original/asm-x86/
pda.h 47 * There is no fast way to get the base address of the PDA, all the accesses
54 * all PDA accesses so it gets read/write dependencies right.
  /external/llvm/test/Analysis/TypeBasedAliasAnalysis/
functionattrs.ll 40 ; that the function accesses memory through its arguments, which TBAA
58 ; Similar to the others, va_arg only accesses memory through its operand.
  /external/oprofile/events/mips/24K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
103 event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
  /external/qemu/memcheck/
memcheck_api.h 67 * retaddr - Code address (in TB) that accesses memory.
83 * retaddr - Code address (in TB) that accesses memory.
  /external/chromium/chrome/browser/ui/cocoa/
browser_test_helper.cc 28 // browser, since it may trigger accesses to the profile upon destruction.
  /external/oprofile/events/x86-64/family12h/
events 15 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
  /external/oprofile/events/x86-64/family14h/
events 15 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
  /external/valgrind/main/helgrind/
README_MSMProp2.txt 146 later-observed accesses: either (1) the accessing thread holds at
147 least one lock in common with LS, or (2) those accesses must
151 Hence a Write state places a constraint on all accesses.
  /external/kernel-headers/original/asm-arm/
io.h 38 * Generic IO read/write. These perform native-endian accesses. Note
69 * Bad read/write accesses...
91 * mapped. Note that these are defined to perform little endian accesses
159 * These perform PCI memory accesses via an ioremap region. They don't
162 * Again, this are defined to perform little endian accesses. See the
  /external/llvm/lib/Analysis/
LoopDependenceAnalysis.cpp 11 // framework, which is used to detect dependences in memory accesses in loops.
43 STATISTIC(NumDependent, "Number of pairs with dependent accesses");
44 STATISTIC(NumIndependent, "Number of pairs with independent accesses");
45 STATISTIC(NumUnknown, "Number of pairs with unknown accesses");
220 // We only analyse loads and stores but no possible memory accesses by e.g.
238 // If the objects noalias, they are distinct, accesses are independent.
243 break; // The underlying objects alias, test accesses for dependence.
  /dalvik/vm/mterp/x86/
entry.S 65 * We're not going to build a standard frame here, so the arg accesses will
  /external/chromium/chrome/browser/content_settings/
content_settings_base_provider.h 127 // Used around accesses to the content_settings_ object to guarantee
  /external/kernel-headers/original/linux/
poll.h 85 * Use "unsigned long" accesses to let user-mode fd_set's be long-aligned.
  /external/llvm/test/Transforms/ScalarRepl/
nonzero-first-index.ll 44 ; ...and again make sure that out-of-range accesses are not transformed.
  /external/oprofile/events/i386/atom/
events 16 event:0x08 counters:0,1 um:data_tlb_misses minimum:6000 name:DATA_TLB_MISSES : Memory accesses that missed the DTLB
32 event:0x2B counters:0,1 um:core,mesi minimum:6000 name:L2_LOCK : L2 locked accesses
38 event:0x40 counters:0,1 um:l1d_cache minimum:6000 name:L1D_CACHE : L1d Cache accesses
62 event:0x80 counters:0,1 um:icache minimum:6000 name:ICACHE : Instruction cache accesses
  /external/webkit/LayoutTests/dom/html/level2/html/
HTMLScriptElement06.js 78 htmlFor is described as for future use. Test accesses the value, but makes no assertions about its value.
HTMLScriptElement07.js 78 event is described as for future use. Test accesses the value, but makes no assertions about its value.

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