| /external/llvm/test/CodeGen/X86/ |
| 2007-03-01-SpillerCrash.ll | 6 fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:0 [#uses=4]
9 fmul <4 x float> %0, %2 ; <<4 x float>>:3 [#uses=1]
11 fmul <4 x float> %4, zeroinitializer ; <<4 x float>>:5 [#uses=2]
57 fmul <4 x float> %34, < float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01 > ; <<4 x float>>:35 [#uses=1]
|
| 2007-11-06-InstrSched.ll | 16 %tmp11 = fmul float %tmp9, %tmp45 ; <float> [#uses=1]
|
| extract-combine.ll | 11 %mul.i25621 = fmul <4 x float> zeroinitializer, %sub.i25620 ; <<4 x float>> [#uses=1]
|
| v-binop-widen2.ll | 33 %nextExpected = fmul float %expected, 2.0
|
| 2008-02-27-DeadSlotElimBug.ll | 27 %tmp17.i76 = fmul double %tmp4344, 0.000000e+00 ; <double> [#uses=1]
32 %tmp17.i63 = fmul double %tmp5051, 0.000000e+00 ; <double> [#uses=1]
38 %tmp17.i = fmul double %tmp5657, %tmp16.i50 ; <double> [#uses=1]
|
| multiple-loop-post-inc.ll | 38 %12 = fmul float %11, %x.0 ; <float> [#uses=1]
60 %19 = fmul float %0, 4.000000e+00 ; <float> [#uses=1]
62 %20 = fmul float %0, 1.600000e+01 ; <float> [#uses=1]
64 %21 = fmul float %0, 0.000000e+00 ; <float> [#uses=1]
67 %24 = fmul float %0, 2.000000e+00 ; <float> [#uses=1]
69 %26 = fmul float %0, 3.000000e+00 ; <float> [#uses=1]
130 %40 = fmul <4 x float> %36, %vX0.039 ; <<4 x float>> [#uses=1]
132 %42 = fmul <4 x float> %37, %vX1.036 ; <<4 x float>> [#uses=1]
133 %43 = fmul <4 x float> %38, %vX2.037 ; <<4 x float>> [#uses=1]
134 %44 = fmul <4 x float> %39, %vX3.041 ; <<4 x float>> [#uses=1
[all...] |
| 2007-04-24-VectorCrash.ll | 32 fmul <4 x float> %22, zeroinitializer ; <<4 x float>>:23 [#uses=1]
38 fmul <4 x float> zeroinitializer, %28 ; <<4 x float>>:29 [#uses=1]
40 fmul <4 x float> zeroinitializer, %30 ; <<4 x float>>:31 [#uses=1]
42 fmul <4 x float> zeroinitializer, %32 ; <<4 x float>>:33 [#uses=1]
44 fmul <4 x float> zeroinitializer, %34 ; <<4 x float>>:35 [#uses=1]
|
| fold-pcmpeqd-2.ll | 42 %mul166.i = fmul <4 x float> zeroinitializer, %sub140.i ; <<4 x float>> [#uses=1]
44 %mul171.i = fmul <4 x float> %add167.i, %sub140.i ; <<4 x float>> [#uses=1]
49 %mul186.i = fmul <4 x float> %bitcast179.i, zeroinitializer ; <<4 x float>> [#uses=1]
55 %mul310 = fmul <4 x float> %bitcast204.i104, zeroinitializer ; <<4 x float>> [#uses=2]
56 %mul313 = fmul <4 x float> %bitcast204.i, zeroinitializer ; <<4 x float>> [#uses=1]
|
| iv-users-in-other-loops.ll | 33 %6 = fmul float %4, %5 ; <float> [#uses=1]
85 %20 = fmul <4 x float> %17, %19 ; <<4 x float>> [#uses=1]
95 %28 = fmul <4 x float> %24, %27 ; <<4 x float>> [#uses=1]
105 %36 = fmul <4 x float> %32, %35 ; <<4 x float>> [#uses=1]
115 %44 = fmul <4 x float> %40, %43 ; <<4 x float>> [#uses=1]
139 %54 = fmul <4 x float> %51, %53 ; <<4 x float>> [#uses=1]
192 %74 = fmul <4 x float> %73, %62 ; <<4 x float>> [#uses=1]
197 %79 = fmul <4 x float> %78, %65 ; <<4 x float>> [#uses=1]
202 %84 = fmul <4 x float> %83, %68 ; <<4 x float>> [#uses=1]
207 %89 = fmul <4 x float> %88, %71 ; <<4 x float>> [#uses=1
[all...] |
| /external/llvm/test/Feature/ |
| ppcld.ll | 18 %tmp3 = fmul double %tmp1, %tmp2 ; <double> [#uses=1]
|
| x86ld.ll | 18 %tmp3 = fmul double %tmp1, %tmp2 ; <double> [#uses=1]
|
| /external/llvm/test/Transforms/InstCombine/ |
| phi-merge-gep.ll | 49 %36 = fmul float %30, -1.500000e+00 ; <float> [#uses=1]
50 %37 = fmul float %31, -1.500000e+00 ; <float> [#uses=1]
53 %40 = fmul float %32, 0x3FEBB67AE0000000 ; <float> [#uses=2]
54 %41 = fmul float %33, 0x3FEBB67AE0000000 ; <float> [#uses=2]
|
| select-crash.ll | 17 %mul91 = fmul double %highlights, %cond90
|
| sqrt.ll | 43 %mul18 = fmul float %tmp14, %tmp14
|
| /external/llvm/test/Transforms/LoopUnroll/ |
| shifted-tripcount.ll | 21 %mul9 = fmul double %tmp8, %tmp4 ; <double> [#uses=1]
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrFP.td | 173 [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
176 [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
181 [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr12:$src2)))]>;
184 [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr12:$src2)))]>;
188 [(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
192 [(set FP32:$dst, (fadd (fmul (load rriaddr12:$src2),
198 [(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
202 [(set FP64:$dst, (fadd (fmul (load rriaddr12:$src2),
208 [(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
212 [(set FP32:$dst, (fsub (fmul (load rriaddr12:$src2)
[all...] |
| /external/quake/quake/src/QW/client/ |
| d_parta.asm | 250 fmul st(0),st(1)
252 fmul st(0),st(3)
254 fmul st(0),st(5)
264 fmul st(0),st(2)
269 fmul st(0),st(4)
271 fmul st(0),st(3)
276 fmul ds:dword ptr[_r_pright+4]
278 fmul ds:dword ptr[_r_pright]
280 fmul ds:dword ptr[_r_pright+8]
285 fmul st(0),st(2)
[all...] |
| d_polysa.asm | 278 fmul st(0),st(5)
281 fmul ds:dword ptr[p01_minus_p21]
283 fmul ds:dword ptr[p10_minus_p20]
285 fmul st(0),st(5)
290 fmul ds:dword ptr[float_minus_1]
292 fmul st(0),st(3)
294 fmul st(0),st(2)
307 fmul st(0),st(6)
310 fmul ds:dword ptr[p01_minus_p21]
312 fmul ds:dword ptr[p10_minus_p20]
[all...] |
| d_spr8.s | 181 fld %st(0) // FIXME: get rid of stall on FMUL?
234 fmul %st(4),%st(0) // s | z*64k | 1/z | t/z | s/z
236 fmul %st(3),%st(0) // t | s | 1/z | t/z | s/z
245 fmul %st(2),%st(0) // _d_zistepu*scm1 | _d_tdivzstepu | scm1
247 fmul %st(2),%st(0) // _d_tdivzstepu*scm1 | _d_zistepu*scm1 | scm1
268 fmul %st(4),%st(0) // s | z*64k | 1/z | t/z | s/z
270 fmul %st(3),%st(0) // t | s | 1/z | t/z | s/z
282 fmul %st(4),%st(0) // s | z*64k | 1/z | t/z | s/z
284 fmul %st(3),%st(0) // t | s | 1/z | t/z | s/z
350 fmul %st(4),%st(0) // s = s/z *
[all...] |
| /external/quake/quake/src/WinQuake/ |
| d_spr8.s | 181 fld %st(0) // FIXME: get rid of stall on FMUL?
234 fmul %st(4),%st(0) // s | z*64k | 1/z | t/z | s/z
236 fmul %st(3),%st(0) // t | s | 1/z | t/z | s/z
245 fmul %st(2),%st(0) // _d_zistepu*scm1 | _d_tdivzstepu | scm1
247 fmul %st(2),%st(0) // _d_tdivzstepu*scm1 | _d_zistepu*scm1 | scm1
268 fmul %st(4),%st(0) // s | z*64k | 1/z | t/z | s/z
270 fmul %st(3),%st(0) // t | s | 1/z | t/z | s/z
282 fmul %st(4),%st(0) // s | z*64k | 1/z | t/z | s/z
284 fmul %st(3),%st(0) // t | s | 1/z | t/z | s/z
350 fmul %st(4),%st(0) // s = s/z *
[all...] |
| /external/llvm/test/Analysis/ScalarEvolution/ |
| scev-aa.ll | 27 %z = fmul double %x, %y
66 %z = fmul double %x, %y
73 %b = fmul double %x, %a
123 %z = fmul double %x, %y
130 %b = fmul double %x, %a
|
| /external/clang/test/CodeGen/ |
| fp16-ops.c | 46 // CHECK: fmul float
52 // CHECK: fmul float
56 // CHECK: fmul float
60 // CHECK: fmul float
256 // CHECK: fmul
261 // CHECK: fmul
265 // CHECK: fmul
|
| /external/llvm/test/CodeGen/ARM/ |
| lsr-on-unrolled-loops.ll | 143 %t90 = fmul float %t88, %t89
158 %t95 = fmul float %t93, %t94
161 %t98 = fmul float %t96, %t97
165 %t102 = fmul float %t100, %t101
169 %t106 = fmul float %t104, %t105
174 %t111 = fmul float %t110, 0x3FF6A09E60000000
182 %t119 = fmul float %t117, %t118
186 %t123 = fmul float %t121, %t122
190 %t127 = fmul float %t125, %t126
194 %t131 = fmul float %t129, %t13
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| 2008-09-12-CoalescerBug.ll | 32 %13 = fmul float %10, 6.553500e+04 ; <float> [#uses=1]
34 %15 = fmul float %12, 6.553500e+04 ; <float> [#uses=1]
71 %40 = fmul float %37, 6.553500e+04 ; <float> [#uses=1]
73 %42 = fmul float %39, 6.553500e+04 ; <float> [#uses=1]
91 %53 = fmul float %50, 6.553500e+04 ; <float> [#uses=1]
93 %55 = fmul float %52, 6.553500e+04 ; <float> [#uses=1]
114 %76 = fmul float %73, 6.553500e+04 ; <float> [#uses=1]
116 %78 = fmul float %75, 6.553500e+04 ; <float> [#uses=1]
137 %89 = fmul float %86, 6.553500e+04 ; <float> [#uses=1]
139 %91 = fmul float %88, 6.553500e+04 ; <float> [#uses=1
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| 2009-12-01-LoopIVUsers.ll | 57 %6 = fmul double %5, 1.500000e+00 ; <double> [#uses=1]
85 %22 = fmul float %20, %21 ; <float> [#uses=1]
98 %30 = fmul double %29, 1.234000e+00 ; <double> [#uses=1]
|
