| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 193 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
194 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
195 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
230 //! Emit the instruction sequence for i64 shl
233 //! Emit the instruction sequence for i64 srl
236 //! Emit the instruction sequence for i64 sra
239 //! Emit the necessary sequence for loading i64 constants:
242 //! Alternate instruction emit sequence for loading i64 constants
592 case MVT::i64:
645 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
[all...] |
| /external/clang/test/CodeGen/ |
| bitfield-2.c | 40 // CHECK-OPT: define i64 @test_0()
41 // CHECK-OPT: ret i64 1
95 // CHECK-OPT: define i64 @test_1()
96 // CHECK-OPT: ret i64 210
140 // CHECK-OPT: define i64 @test_2()
141 // CHECK-OPT: ret i64 2
176 // CHECK-OPT: define i64 @test_3()
177 // CHECK-OPT: ret i64 -559039940
210 // CHECK-OPT: define i64 @test_4()
211 // CHECK-OPT: ret i64 486
[all...] |
| /external/clang/test/CodeGenCXX/ |
| x86_32-arguments.cpp | 60 // CHECK: define i64 @_Z2f0v()
81 // CHECK: define i64 @_Z2f4v()
92 // CHECK: define i64 @_Z4f6_1M2s6FivE({ i32, i32 }* byval align 4)
|
| delete-two-arg.cpp | 32 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds i8* [[NEW]], i64 4
46 // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8* [[T2]], i64 -4
|
| new-overflow.cpp | 170 // CHECK: define [[A:%.*]]* @_ZN5test84testEx(i64
171 // CHECK: [[N:%.*]] = load i64*
172 // CHECK-NEXT: [[T0:%.*]] = icmp uge i64 [[N]], 4294967296
173 // CHECK-NEXT: [[T1:%.*]] = trunc i64 [[N]] to i32
195 // CHECK: define [[A:%.*]]* @_ZN5test94testEy(i64
196 // CHECK: [[N:%.*]] = load i64*
197 // CHECK-NEXT: [[T0:%.*]] = icmp uge i64 [[N]], 4294967296
198 // CHECK-NEXT: [[T1:%.*]] = trunc i64 [[N]] to i32
|
| /external/llvm/test/Analysis/BasicAA/ |
| intrinsics.ll | 3 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
24 ; CHECK-NEXT: %q = getelementptr i8* %p, i64 16
30 %q = getelementptr i8* %p, i64 16
|
| /external/llvm/test/CodeGen/ARM/ |
| vaba.ll | 175 define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
178 %tmp1 = load <2 x i64>* %A
182 %tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
183 %tmp6 = add <2 x i64> %tmp1, %tmp5
184 ret <2 x i64> %tmp6
211 define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
214 %tmp1 = load <2 x i64>* %A
218 %tmp5 = zext <2 x i32> %tmp4 to <2 x i64>
[all...] |
| pr3502.ll | 4 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
7 %struct.SHARED_AREA = type { i32, %struct.SHARED_AREA*, %struct.SHARED_AREA*, %struct.SHARED_AREA*, %struct.ArmPTD, void (%struct.RegisterSave*)*, void (%struct.RegisterSave*)*, i32, [1024 x i8], i32, i32, i32, i32, i32, i8, i8, i16, i32, i32, i32, i32, [16 x i8], i32, i32, i32, i8, i8, i8, i32, i16, i32, i64, i32, i32, i32, i32, i32, i32, i8*, i32, [256 x i8], i32, i32, i32, [20 x i8], %struct.RegisterSave, { %struct.WorldSwitchV5 }, [4 x i32] }
|
| vld3.ll | 8 %struct.__neon_int64x1x3_t = type { <1 x i64>, <1 x i64>, <1 x i64> }
74 define <1 x i64> @vld3i64(i64* %A) nounwind {
78 %tmp0 = bitcast i64* %A to i8*
82 %tmp4 = add <1 x i64> %tmp2, %tmp3
83 ret <1 x i64> %tmp4
|
| /external/llvm/test/CodeGen/X86/ |
| 2011-04-13-SchedCmpJmp.ll | 22 %tobool.i.i.i = icmp ugt i8* undef, inttoptr (i64 281474976710655 to i8*)
30 %conv.i.i.i.i = trunc i64 undef to i32
56 %2 = getelementptr inbounds i8** %args, i64 -1
|
| avoid-loop-align-2.ll | 28 %tmp. = zext i32 %tmp17 to i64 ; <i64> [#uses=1]
29 %3 = getelementptr i32* %2, i64 %tmp. ; <i32*> [#uses=1]
|
| 2006-10-12-CycleInDAG.ll | 7 %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
8 %struct.tree_decl_u1 = type { i64 }
|
| 2008-02-27-PEICrash.ll | 3 define i64 @__divsc3(float %a, float %b, float %c, float %d) nounwind readnone {
32 ret i64 0
|
| 2008-05-21-CoalescerBug.ll | 18 %struct.basic_block_def = type { %struct.tree_node*, %struct.VEC_edge_gc*, %struct.VEC_edge_gc*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_il_dependent, %struct.tree_node*, %struct.edge_prediction*, i64, i32, i32, i32, i32 }
23 %struct.block_symbol = type { [3 x %struct.cfg_stats_d], %struct.object_block*, i64 }
27 %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.__sbuf*, i32, i32, i64, i32 }
34 %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.control_flow_graph*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.VEC_temp_slot_p_gc*, %struct.temp_slot*, %struct.var_refs_queue*, i32, i32, i32, i32, %struct.machine_function*, i32, i32, %struct.language_function*, %struct.htab*, %struct.rtx_def*, i32, i32, i32, %struct.__sbuf, %struct.VEC_tree_gc*, %struct.tree_node*, i8*, i8*, i8*, i8*, i8*, %struct.tree_node*, i8, i8, i8, i8, i8, i8 }
43 %struct.object_block = type { %struct.section*, i32, i64, %struct.VEC_rtx_gc*, %struct.VEC_rtx_gc* }
56 %struct.tree_decl_common = type { %struct.tree_decl_minimal, %struct.tree_node*, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }
59 %struct.tree_decl_u1 = type { i64 }
62 %struct.tree_function_decl = type { %struct.tree_decl_non_common, i8, i8, i64, %struct.function* }
|
| /external/llvm/test/Transforms/GVN/ |
| 2010-05-08-OneBit.ll | 4 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
9 %0 = getelementptr inbounds i8* undef, i64 5 ; <i8*> [#uses=1]
32 %2 = getelementptr i8* undef, i64 5 ; <i8*> [#uses=1]
|
| 2011-04-27-phioperands.ll | 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
30 store i8* getelementptr inbounds ([10 x i8]* @nuls, i64 0, i64 0), i8** undef, align 8
|
| /external/llvm/test/Transforms/GlobalOpt/ |
| heap-sra-phi.ll | 3 target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
10 %malloccall = tail call i8* @malloc(i64 8000000) ; <i8*> [#uses=1]
17 declare noalias i8* @malloc(i64)
|
| /external/llvm/test/Transforms/InstCombine/ |
| or.ll | 4 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
325 define i64 @test31(i64 %A) nounwind readnone ssp noredzone {
326 %B = or i64 %A, 194
327 %D = and i64 %B, 250
329 %C = or i64 %A, 32768
330 %E = and i64 %C, 4294941696
332 %F = or i64 %D, %E
333 ret i64 %F
335 ; CHECK-NEXT: %E = and i64 %A, 429490898
[all...] |
| rem.ll | 66 %tmp.3 = sext i32 %tmp.2 to i64
67 %tmp.5 = urem i64 %tmp.3, 4
68 %tmp.6 = trunc i64 %tmp.5 to i32
|
| simplify-demanded-bits-pointer.ll | 5 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
9 %struct.block_symbol = type { [3 x %struct.rtunion], %struct.object_block*, i64 }
10 %struct.object_block = type { %struct.section*, i32, i64, %struct.VEC_rtx_gc*, %struct.VEC_rtx_gc* }
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| 2005-08-15-AddRecIV.ll | 52 %gep.upgrd.1 = zext i32 %tmp. to i64 ; <i64> [#uses=1]
53 %tmp.528 = getelementptr i32* %tmp.526, i64 %gep.upgrd.1 ; <i32*> [#uses=1]
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetMachine.cpp | 56 std::string("e-p:32:32-f64:32:64-i64:32:64-"
59 std::string("e-p:32:32-f64:64:64-i64:64:64-"
61 std::string("e-p:32:32-f64:64:64-i64:64:64-"
80 std::string("e-p:32:32-f64:32:64-i64:32:64-"
84 std::string("e-p:32:32-f64:64:64-i64:64:64-"
87 std::string("e-p:32:32-f64:64:64-i64:64:64-"
|
| /external/llvm/lib/Target/Sparc/ |
| SparcSubtarget.h | 48 p = "E-p:64:64:64-i64:64:64-f64:64:64-f128:128:128-n32:64";
50 p = "E-p:32:32:32-i64:64:64-f64:64:64-f128:64:64-n32";
|
| /external/llvm/test/CodeGen/Generic/ |
| badarg6.ll | 30 %reg609 = call i32 (i8*, ...)* @printf( i8* getelementptr ([44 x i8]* @.LC12, i64 0, i64 0), double %reg325, double %reg324, double %reg323, double %reg322, double %reg321 ) ; <i32> [#uses=0]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| vec_misaligned.ll | 3 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
21 %tmp3 = getelementptr i8* %tmp2, i64 16 ; <i8*> [#uses=1]
|
