| /external/clang/test/CodeGenObjC/ |
| arc.m | 185 // CHECK-NEXT: load i64* @"OBJC_IVAR_$_Test5.var"
196 // CHECK-NEXT: load i64* @"OBJC_IVAR_$_Test5.var"
425 // CHECK-NEXT: [[Y_OFF:%.*]] = load i64* @"OBJC_IVAR_$_Test16.y"
427 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds i8* [[T0]], i64 [[Y_OFF]]
432 // CHECK-NEXT: [[Z_OFF:%.*]] = load i64* @"OBJC_IVAR_$_Test16.z"
434 // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds i8* [[T0]], i64 [[Z_OFF]]
461 // CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[T0]], i8 0, i64 40, i32 16, i1 false)
469 // CHECK-NEXT: [[SLOT:%.*]] = getelementptr inbounds [5 x i8*]* [[X]], i32 0, i64 2
475 // CHECK-NEXT: [[END:%.*]] = getelementptr inbounds i8** [[BEGIN]], i64
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| ppc32-vaarg.ll | 3 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
8 @var1 = common global i64 0, align 8
14 %x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6
67 store i64 %x, i64* @var1, align 8
|
| /external/icu4c/test/iotest/ |
| iotest.cpp | 213 int64_t i64; local
277 i64 = uto64(argument);
278 uBufferLenReturned = u_sprintf_u(uBuffer, format, i64);
279 uFileBufferLenReturned = u_fprintf_u(testFile.getAlias(), format, i64);
378 int64_t i64, expected64; local
468 uBufferLenReturned = u_sscanf_u(argument, format, &i64);
469 //uFileBufferLenReturned = u_fscanf_u(testFile, format, i64);
470 if (i64 != expected64) {
582 int64_t i64; local
633 i64 = uto64(argument)
[all...] |
| /external/clang/test/CodeGenCXX/ |
| destructors.cpp | 241 // CHECK-NEXT: [[END:%.*]] = getelementptr inbounds [[A]]* [[BEGIN]], i64 5
244 // CHECK-NEXT: [[ELT]] = getelementptr inbounds [[A]]* [[POST]], i64 -1
253 // CHECK-NEXT: [[CUR:%.*]] = getelementptr inbounds [[A]]* [[AFTER]], i64 -1
369 // CHECK: getelementptr inbounds i8* {{.*}}, i64 -8
374 // CHECK: getelementptr inbounds i8* {{.*}}, i64 -8
396 // CHECK: getelementptr inbounds i8* {{.*}}, i64 -8
401 // CHECK: getelementptr inbounds i8* {{.*}}, i64 -8
|
| eh.cpp | 13 // CHECK: [[EXNOBJ:%.*]] = call i8* @__cxa_allocate_exception(i64 8)
16 // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[EXN2]], i8* bitcast ([[DSTAR]] @d1 to i8*), i64 8, i32 8, i1 false)
35 // CHECK-NEXT: [[EXNOBJ:%.*]] = call i8* @__cxa_allocate_exception(i64 16)
55 // CHECK: [[EXNOBJ:%.*]] = call i8* @__cxa_allocate_exception(i64 8)
83 // CHECK: [[EXNOBJ:%.*]] = call i8* @__cxa_allocate_exception(i64 1)
424 // CHECK: [[EXN:%.*]] = call i8* @__cxa_allocate_exception(i64 4)
|
| temporaries.cpp | 332 // CHECK: call void @llvm.memset.p0i8.i64
335 // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64
428 // CHECK-NEXT: [[XS0:%.*]] = getelementptr inbounds [2 x [[A]]]* [[XS]], i64 0, i64 0
430 // CHECK-NEXT: [[XS1:%.*]] = getelementptr inbounds [[A]]* [[XS0]], i64 1
435 // CHECK-NEXT: [[END:%.*]] = getelementptr inbounds [[A]]* [[BEGIN]], i64 2
438 // CHECK-NEXT: [[CUR:%.*]] = getelementptr inbounds [[A]]* [[AFTER]], i64 -1
|
| unknown-anytype.cpp | 53 // CHECK: call i64 @test6_any(float* null)
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrLoadStore.td | 73 def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
75 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
77 def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
79 def ADDRlocal64 : ComplexPattern<i64, 2, "SelectADDRlocal", [], []>;
86 def MEMri64 : Operand<i64> {
94 def LOCALri64 : Operand<i64> {
102 def MEMii64 : Operand<i64> {
|
| /external/llvm/test/Transforms/InstCombine/ |
| shufflemask-undef.ll | 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
5 %struct.ActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaInstrInfo.td | 33 def SDT_AlphaCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64> ]>;
34 def SDT_AlphaCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i64>,
35 SDTCisVT<1, i64> ]>;
506 def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
508 def : Pat<(i64 (sextloadi32 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
510 def : Pat<(i64 (zextloadi8 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
512 def : Pat<(i64 (zextloadi16 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
514 def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)),
516 def : Pat<(i64 (Alpha_gprelhi tconstpool:$DISP, GPRC:$RB)),
524 def : Pat<(i64 (Alpha_gprelhi tjumptable:$DISP, GPRC:$RB))
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| vabd.ll | 169 define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
175 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
176 ret <2 x i64> %tmp4
199 define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
205 %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
206 ret <2 x i64> %tmp4
|
| 2007-08-15-ReuseBug.ll | 4 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
|
| /external/icu4c/test/intltest/ |
| winnmtst.cpp | 236 int64_t i64 = randomInt64(); local
242 getWindowsFormat(lcid, currency, w6Buffer, L"%I64d", i64);
260 wnf->format(i64, u6Buffer);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.td | 173 def GR64 : RegisterClass<"SystemZ", [i64], 64, (add (sequence "R%uD", 0, 5),
178 def ADDR64 : RegisterClass<"SystemZ", [i64], 64, (sub GR64, R0D)> {
203 def CCR : RegisterClass<"SystemZ", [i64], 64, (add PSW)> {
|
| /external/llvm/test/CodeGen/Thumb2/ |
| 2010-06-21-TailMergeBug.ll | 5 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
|
| /external/llvm/test/CodeGen/X86/ |
| 2007-02-16-BranchFold.ll | 7 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
|
| scev-interchange.ll | 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
14 %"struct.std::_Bit_iterator_base" = type { i64*, i32 }
16 %"struct.std::_Bvector_base<std::allocator<bool> >::_Bvector_impl" = type { %"struct.std::_Bit_const_iterator", %"struct.std::_Bit_const_iterator", i64* }
34 declare i8* @_Znwm(i64)
40 declare fastcc void @_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_(%"struct.std::vector<bool,std::allocator<bool> >"* nocapture, i64, i8* nocapture)
42 declare fastcc void @_ZNSt6vectorIS_IbSaIbEESaIS1_EEC2EmRKS1_RKS2_(%"struct.std::vector<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >"* nocapture, i64, %"struct.std::vector<bool,std::allocator<bool> >"* nocapture)
56 invoke fastcc void @_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_(%"struct.std::vector<bool,std::allocator<bool> >"* undef, i64 1, i8* undef)
64 invoke fastcc void @_ZNSt6vectorIS_IbSaIbEESaIS1_EEC2EmRKS1_RKS2_(%"struct.std::vector<std::vector<bool, std::allocator<bool> >,std::allocator<std::vector<bool, std::allocator<bool> > > >"* undef, i64 undef, %"struct.std::vector<bool,std::allocator<bool> >"* undef)
72 invoke fastcc void @_ZNSt6vectorIbSaIbEEC1EmRKbRKS0_(%"struct.std::vector<bool,std::allocator<bool> >"* undef, i64 undef, i8* undef)
148 %tmp11.i.i29.i.i.i.i.i.i = invoke i8* @_Znwm(i64 12
[all...] |
| /external/expat/examples/ |
| outline.c | 34 #define XML_FMT_INT_MOD "I64"
|
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 42 i64 = 5, // This is a 64 bit integer value enumerator in enum:llvm::MVT::SimpleValueType
66 v1i64 = 24, // 1 x i64
67 v2i64 = 25, // 2 x i64
68 v4i64 = 26, // 4 x i64
69 v8i64 = 27, // 8 x i64
205 case v8i64: return i64;
262 case i64 :
328 return MVT::i64;
356 case MVT::i64:
|
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.td | 55 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
94 // i64/f64 is passed in even pairs of GPRs
95 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
110 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
|
| /external/llvm/lib/Target/MSP430/ |
| README.txt | 28 6. Verify and fix (if needed) how's stuff playing with i32 / i64.
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstr64Bit.td | 18 def s16imm64 : Operand<i64> {
21 def u16imm64 : Operand<i64> {
24 def symbolHi64 : Operand<i64> {
28 def symbolLo64 : Operand<i64> {
81 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
107 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
119 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
121 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
124 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
126 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst))
[all...] |
| /external/llvm/lib/Target/ |
| README.txt | 573 call void @llvm.memset.p0i8.i64(i8* %tmp, i8 0, i64 64, i32 16, i1 false)
574 %0 = getelementptr [8 x i64]* %input, i64 0, i64 0
575 store i64 1, i64* %0, align 16
576 %1 = getelementptr [8 x i64]* %input, i64 0, i64
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 102 AVT = MVT::i64;
148 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
149 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
212 AVT = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreTargetMachine.cpp | 28 "i16:16:32-i32:32:32-i64:32:32-n32"),
|
