| /external/llvm/test/CodeGen/Generic/ |
| APIntParam.ll | 65 @i64_s = external global i64 ; <i64*> [#uses=1]
574 define void @i64_ls(i64 %x) nounwind {
575 store i64 %x, i64* @i64_s
[all...] |
| APIntSextParam.ll | 65 @i64_s = external global i64 ; <i64*> [#uses=1]
574 define void @i64_ls(i64 signext %x) nounwind {
575 store i64 %x, i64* @i64_s
[all...] |
| APIntZextParam.ll | 65 @i64_s = external global i64 ; <i64*> [#uses=1]
574 define void @i64_ls(i64 zeroext %x) nounwind {
575 store i64 %x, i64* @i64_s
[all...] |
| 2006-06-28-SimplifySetCCCrash.ll | 2 %struct.rtunion = type { i64 }
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 638 /// %B = trunc i64 %A to i32
640 /// %E = zext i32 %C to i64
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 82 // bitcast (<2 x i64> <i64 0, i64 1> to <4 x i32>)
124 // Handle: bitcast (<4 x i32> <i32 0, i32 1, i32 2, i32 3> to <2 x i64>)
152 // Handle: bitcast (<2 x i64> <i64 0, i64 1> to <4 x i32>)
[all...] |
| TypeBasedAliasAnalysis.cpp | 24 // !3 = metadata !{ metadata !"const float", metadata !2, i64 1 }
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 377 if (RetVT == MVT::i64)
388 if (RetVT == MVT::i64)
395 if (RetVT == MVT::i64)
402 if (RetVT == MVT::i64)
420 if (RetVT == MVT::i64)
431 if (RetVT == MVT::i64)
438 if (RetVT == MVT::i64)
445 if (RetVT == MVT::i64)
465 } else if (OpVT == MVT::i64) {
499 } else if (OpVT == MVT::i64) {
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_ppc_isel.c | 129 fcfid[.] (i64->dbl) if . y y
132 fctid[.] (dbl->i64) if . ->undef y
133 fctidz[.] (dbl->i64) if . ->undef rounds-to-zero
342 64-bit mode: compute an I8/I16/I32/I64 into a GPR. */
348 64-bit mode: Compute an I8/I16/I32/I64 into a RH
361 64-bit mode: compute an I64 into a RI (reg or 64-bit immediate). */
378 64-bit mode: compute an I64 into an AMode.
391 /* 32-bit mode ONLY: compute an I64 into a GPR pair. */
497 /* Load I64 reg to fp reg */
650 In fact the only supported arg type is (mode32:I32 | mode64:I64)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 98 setOperationAction(ISD::ADD, MVT::i64, Custom);
99 setOperationAction(ISD::SUB, MVT::i64, Custom);
124 // Conversion of i64 -> double produces constantpool nodes
678 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
686 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
701 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
707 assert(N->getValueType(0) == MVT::i64 &&
741 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| neont2.txt | 118 # CHECK: vadd.i64 d16, d17, d16
240 # CHECK: vaddhn.i64 d16, q8, q9
246 # CHECK: vraddhn.i64 d16, q8, q9
493 # CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF
513 # CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF
547 # CHECK: vmovn.i64 d16, q8
1034 # CHECK: vshl.i64 d16, d16, #63
1050 # CHECK: vshl.i64 q8, q8, #63
1106 # CHECK: vshrn.i64 d16, q8, #32
1176 # CHECK: vrshrn.i64 d16, q8, #3
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| 2008-07-15-Bswap.ll | 2 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
386 declare void @llvm.memset.i64(i8*, i8, i64, i32) nounwind
|
| /external/clang/include/clang/Basic/ |
| BuiltinsX86.def | 62 // types (<1 x i64>, <2 x i32>, etc.) that aren't used by these builtins will be
|
| /external/clang/lib/CodeGen/ |
| CGRecordLayout.h | 84 /// separate components to support up to i64 bit-field access (4 + 2 + 1 byte
|
| /external/llvm/docs/ |
| ExtendedIntegerResults.txt | 110 that extends results to i64, no i32). This solves the ambiguity issue, allows us
|
| /external/llvm/lib/Target/Blackfin/ |
| README.txt | 110 to return i64, and the code generator doesn't know how to legalize that.
|
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.td | 164 def R64C : RegisterClass<"SPU", [i64], 128, (add GPRC)>;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrAltivec.td | 592 (DST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
594 (DSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
596 (DSTST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
598 (DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
[all...] |
| /external/llvm/lib/Target/X86/ |
| README-X86-64.txt | 11 unsigned i64?
|
| /external/llvm/test/CodeGen/ARM/ |
| vget_lane.ll | 2 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
|
| /external/llvm/test/CodeGen/CellSPU/ |
| eqv.ll | 13 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
|
| intrinsics_branch.ll | 10 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
|
| rotate_ops.ll | 13 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
|
| /external/llvm/test/CodeGen/X86/ |
| 2007-04-24-VectorCrash.ll | 2 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
|
| 2009-08-06-branchfolder-crash.ll | 4 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
|
