| /external/llvm/test/Bitcode/ |
| sse42_crc32.ll | 9 ; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
10 ; CHECK-NOT: i32 @llvm.x86.sse42.crc32.8(
13 ; CHECK: i32 @llvm.x86.sse42.crc32.32.16(
14 ; CHECK-NOT: i32 @llvm.x86.sse42.crc32.16(
17 ; CHECK: i32 @llvm.x86.sse42.crc32.32.32(
18 ; CHECK-NOT: i32 @llvm.x86.sse42.crc32.32(
21 ; CHECK: i64 @llvm.x86.sse42.crc32.64.8(
22 ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.8(
25 ; CHECK: i64 @llvm.x86.sse42.crc32.64.64(
26 ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| byval.ll | 1 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck -check-prefix=X86-64 %s
3 ; RUN: llc < %s -march=x86 | FileCheck -check-prefix=X86 %s
5 ; X86: movl 4(%esp), %eax
6 ; X86: movl 8(%esp), %edx
8 ; X86-64: movq 8(%rsp), %rax
|
| 2004-02-14-InefficientStackPointer.ll | 1 ; RUN: llc < %s -march=x86 | grep -i ESP | not grep sub
|
| 2007-02-25-FastCCStack.ll | 1 ; RUN: llc < %s -march=x86 -mcpu=pentium3
|
| barrier.ll | 1 ; RUN: llc < %s -march=x86 -mattr=-sse2 | grep lock
|
| i128-immediate.ll | 1 ; RUN: llc < %s -march=x86-64 | grep movq | count 2
|
| lea-2.ll | 1 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
3 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
|
| /dalvik/vm/mterp/x86/ |
| OP_ADD_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"addl (rFP,%ecx,4),rIBASE", "instr2":"adcl 4(rFP,%ecx,4),%eax"}
|
| OP_ADD_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"addl %eax,(rFP,rINST,4)","instr2":"adcl %ecx,4(rFP,rINST,4)"}
|
| OP_AND_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"andl (rFP,%ecx,4),rIBASE", "instr2":"andl 4(rFP,%ecx,4),%eax"}
|
| OP_AND_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"andl %eax,(rFP,rINST,4)","instr2":"andl %ecx,4(rFP,rINST,4)"}
|
| OP_IGET_BYTE.S | 3 %include "x86/OP_IGET.S" { "load":"movsbl", "sqnum":"2" }
|
| OP_IGET_BYTE_JUMBO.S | 3 %include "x86/OP_IGET_JUMBO.S" { "load":"movsbl", "sqnum":"2" }
|
| OP_IGET_CHAR.S | 3 %include "x86/OP_IGET.S" { "load":"movzwl", "sqnum":"3" }
|
| OP_IGET_CHAR_JUMBO.S | 3 %include "x86/OP_IGET_JUMBO.S" { "load":"movzwl", "sqnum":"3" }
|
| OP_IGET_SHORT.S | 3 %include "x86/OP_IGET.S" { "load":"movswl", "sqnum":"4" }
|
| OP_IGET_SHORT_JUMBO.S | 3 %include "x86/OP_IGET_JUMBO.S" { "load":"movswl", "sqnum":"4" }
|
| OP_LONG_TO_INT.S | 3 %include "x86/OP_MOVE.S"
|
| OP_OR_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"orl (rFP,%ecx,4),rIBASE", "instr2":"orl 4(rFP,%ecx,4),%eax"}
|
| OP_OR_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"orl %eax,(rFP,rINST,4)","instr2":"orl %ecx,4(rFP,rINST,4)"}
|
| OP_SUB_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"subl (rFP,%ecx,4),rIBASE", "instr2":"sbbl 4(rFP,%ecx,4),%eax"}
|
| OP_SUB_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"subl %eax,(rFP,rINST,4)","instr2":"sbbl %ecx,4(rFP,rINST,4)"}
|
| OP_XOR_LONG.S | 2 %include "x86/binopWide.S" {"instr1":"xorl (rFP,%ecx,4),rIBASE", "instr2":"xorl 4(rFP,%ecx,4),%eax"}
|
| OP_XOR_LONG_2ADDR.S | 2 %include "x86/binopWide2addr.S" {"instr1":"xorl %eax,(rFP,rINST,4)","instr2":"xorl %ecx,4(rFP,rINST,4)"}
|
| /external/llvm/test/CodeGen/CBackend/X86/ |
| dg.exp | 3 if { [llvm_supports_target X86] && [llvm_supports_target CBackend] } {
|
