/external/llvm/test/CodeGen/X86/ |
epilogue.ll | 1 ; RUN: llc < %s -march=x86 | not grep lea 2 ; RUN: llc < %s -march=x86 | grep {movl %ebp}
|
fast-cc-merge-stack-adj.ll | 1 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
|
fildll.ll | 1 ; RUN: llc < %s -march=x86 -x86-asm-syntax=att -mattr=-sse2 | grep fildll | count 2
|
fmul-zero.ll | 1 ; RUN: llc < %s -march=x86-64 -enable-unsafe-fp-math | not grep mulps 2 ; RUN: llc < %s -march=x86-64 | grep mulps
|
fold-call.ll | 1 ; RUN: llc < %s -march=x86 | not grep mov 2 ; RUN: llc < %s -march=x86-64 | not grep mov
|
fold-imm.ll | 1 ; RUN: llc < %s -march=x86 | grep inc 2 ; RUN: llc < %s -march=x86 | grep add | grep 4
|
h-registers-3.ll | 1 ; RUN: llc < %s -march=x86 | grep mov | count 1 2 ; RUN: llc < %s -march=x86-64 | grep mov | count 1
|
subreg-to-reg-0.ll | 1 ; RUN: llc < %s -march=x86-64 | grep mov | count 1 4 ; x86-64's implicit zero-extension!
|
vec_shift3.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllq 2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw 3 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 2 7 %tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 %bits ) nounwind readnone ; <<2 x i64>> [#uses=1] 13 %tmp3 = tail call <2 x i64> @llvm.x86.sse2.pslli.q( <2 x i64> %x1, i32 10 ) nounwind readnone ; <<2 x i64>> [#uses=1] 20 %tmp4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w( <8 x i16> %tmp2, i32 %bits ) nounwind readnone ; <<8 x i16>> [#uses=1] 25 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone 26 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
|
mmx-punpckhdq.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse42 -mtriple=x86_64-apple-darwin10 | FileCheck %s 13 tail call void @llvm.x86.mmx.emms( ) 24 %tmp9 = tail call x86_mmx @llvm.x86.mmx.punpckhdq (x86_mmx %tmp2, x86_mmx %tmp2) 26 tail call void @llvm.x86.mmx.emms( ) 30 declare x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx, x86_mmx) 31 declare void @llvm.x86.mmx.emms()
|
bmi.ll | 1 ; RUN: llc < %s -march=x86-64 -mattr=+bmi,+bmi2 | FileCheck %s 56 %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y) 62 declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone 65 %tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y) 71 declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone 74 %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y) 80 declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) nounwind readnone 83 %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y) 89 declare i64 @llvm.x86.bmi.bzhi.64(i64, i64) nounwind readnone 92 %tmp = tail call i32 @llvm.x86.bmi.blsi.32(i32 %x [all...] |
avx-intrinsics-x86.ll | 1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7 -mattr=avx | FileCheck %s 5 %res = call <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] 8 declare <2 x i64> @llvm.x86.aesni.aesdec(<2 x i64>, <2 x i64>) nounwind readnone 13 %res = call <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] 16 declare <2 x i64> @llvm.x86.aesni.aesdeclast(<2 x i64>, <2 x i64>) nounwind readnone 21 %res = call <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] 24 declare <2 x i64> @llvm.x86.aesni.aesenc(<2 x i64>, <2 x i64>) nounwind readnone 29 %res = call <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] 32 declare <2 x i64> @llvm.x86.aesni.aesenclast(<2 x i64>, <2 x i64>) nounwind readnone 37 %res = call <2 x i64> @llvm.x86.aesni.aesimc(<2 x i64> %a0) ; <<2 x i64>> [#uses=1 [all...] |
vec_shift.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psllw 2 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psrlq 3 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep psraw 9 %tmp9 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp8, <8 x i16> %tmp6 ) nounwind readnone ; <<8 x i16>> [#uses=1] 19 %tmp9 = tail call <8 x i16> @llvm.x86.sse2.psra.w( <8 x i16> %tmp2, <8 x i16> %tmp8 ) ; <<8 x i16>> [#uses=1] 24 declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone 28 %tmp9 = tail call <2 x i64> @llvm.x86.sse2.psrl.q( <2 x i64> %b1, <2 x i64> %c ) nounwind readnone ; <<2 x i64>> [#uses=1] 32 declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone 34 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
|
vec_shift2.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep CPI 5 %tmp2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp1, <8 x i16> bitcast (<4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > to <8 x i16>) ) nounwind readnone 12 %tmp2 = tail call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> %tmp1, <4 x i32> < i32 14, i32 undef, i32 undef, i32 undef > ) nounwind readnone 16 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone 17 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
|
3dnow-intrinsics.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+3dnow | FileCheck %s 10 %4 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %2, x86_mmx %3) 15 declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone 21 %1 = tail call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %0) 26 declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone 33 %2 = tail call x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx %0, x86_mmx %1) 38 declare x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx, x86_mmx) nounwind readnone 45 %2 = tail call x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx %0, x86_mmx %1) 50 declare x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx, x86_mmx) nounwind readnone 57 %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx %0, x86_mmx %1 [all...] |
/dalvik/vm/ |
dalvik | 21 ANDROID_ROOT=$ANDROID_BUILD_TOP/out/host/linux-x86 \ 22 LD_LIBRARY_PATH=$ANDROID_BUILD_TOP/out/host/linux-x86/lib \ 23 $ANDROID_BUILD_TOP/out/host/linux-x86/bin/dalvikvm \ 25 :$ANDROID_BUILD_TOP/out/host/linux-x86/framework/core-hostdex.jar\ 26 :$ANDROID_BUILD_TOP/out/host/linux-x86/framework/bouncycastle-hostdex.jar\ 27 :$ANDROID_BUILD_TOP/out/host/linux-x86/framework/apache-xml-hostdex.jar \
|
/external/valgrind/main/none/tests/x86/ |
Makefile.am | 27 bug125959-x86.stderr.exp bug125959-x86.stdout.exp bug125959-x86.vgtest \ 28 bug126147-x86.stderr.exp bug126147-x86.stdout.exp bug126147-x86.vgtest \ 29 bug132813-x86.stderr.exp bug132813-x86.stdout.exp bug132813-x86.vgtest \ 30 bug135421-x86.stderr.exp bug135421-x86.stdout.exp bug135421-x86.vgtest [all...] |
/external/libvpx/vp8/ |
vp8cx.mk | 92 VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/encodemb_x86.h 93 VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/dct_x86.h 94 VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/mcomp_x86.h 95 VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/variance_x86.h 96 VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/quantize_x86.h 97 VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/temporal_filter_x86.h 98 VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/x86_csystemdependent.c 99 VP8_CX_SRCS-$(HAVE_MMX) += encoder/x86/variance_mmx.c 100 VP8_CX_SRCS-$(HAVE_MMX) += encoder/x86/variance_impl_mmx.asm 101 VP8_CX_SRCS-$(HAVE_MMX) += encoder/x86/sad_mmx.as [all...] |
/external/llvm/test/Assembler/ |
AutoUpgradeIntrinsics.ll | 5 declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readnone 6 declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readnone 7 declare <2 x double> @llvm.x86.sse2.loadu.pd(double*) nounwind readnone 9 %v0 = call <4 x float> @llvm.x86.sse.loadu.ps(i8* %a) 10 %v1 = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a) 11 %v2 = call <2 x double> @llvm.x86.sse2.loadu.pd(double* %b) 19 declare void @llvm.x86.sse.movnt.ps(i8*, <4 x float>) nounwind readnone 20 declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x double>) nounwind readnone 21 declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind readnone 22 declare void @llvm.x86.sse2.movnt.i(i8*, i32) nounwind readnone [all...] |
/ndk/docs/ |
CPU-X86.html | 1 <html><body><pre>Android NDK x86 (a.k.a. IA-32) instruction set support 7 Android NDK r6 added support for the 'x86' ABI, that allows native code to 11 The Android x86 ABI itself is fully specified in docs/CPU-ARCH-ABIS.html. 16 Generating x86 machine code is simple: just add 'x86' to your APP_ABI 19 APP_ABI := armeabi armeabi-v7a x86 32 As you would expect, generated libraries will go into $PROJECT/libs/x86/, and 33 will be embedded into your .apk under /lib/x86/. 36 libraries on a *compatible* x86-based device automatically at install time, 48 It is possible to use the x86 toolchain with NDK r6 in stand-alone mode [all...] |
/external/llvm/lib/Target/X86/ |
X86FrameLowering.cpp | 1 //=======- X86FrameLowering.cpp - X86 Frame Information --------*- C++ -*-====// 10 // This file contains the X86 implementation of TargetFrameLowering class. 61 return X86::SUB64ri8; 62 return X86::SUB64ri32; 65 return X86::SUB32ri8; 66 return X86::SUB32ri; 73 return X86::ADD64ri8; 74 return X86::ADD64ri32; 77 return X86::ADD32ri8; 78 return X86::ADD32ri [all...] |
/external/oprofile/m4/ |
configmodule.m4 | 43 AC_MSG_CHECKING(for x86 architecture) 44 AX_KERNEL_OPTION(CONFIG_X86, x86=1, x86=0) 45 AX_KERNEL_OPTION(CONFIG_X86_WP_WORKS_OK, x86=1, x86=$x86) 46 AX_MSG_RESULT_YN($x86) 47 test "$x86" = 1 && arch="x86"
|
/external/clang/test/Driver/ |
apple-kext-mkernel.c | 3 // RUN: FileCheck --check-prefix=CHECK-X86 < %t %s 5 // CHECK-X86: "-disable-red-zone" 6 // CHECK-X86: "-fno-builtin" 7 // CHECK-X86: "-fno-rtti" 8 // CHECK-X86: "-fno-common"
|
/external/llvm/lib/ExecutionEngine/JIT/ |
Makefile | 16 # Enable the X86 JIT if compiling on X86 17 ifeq ($(ARCH), x86) 22 # of the X86 JIT on non-X86 hosts
|
/external/llvm/include/llvm/ |
IntrinsicsX86.td | 1 //===- IntrinsicsX86.td - Defines X86 intrinsics -----------*- tablegen -*-===// 10 // This file defines all of the X86-specific intrinsics. 16 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". 23 let TargetPrefix = "x86" in { 82 let TargetPrefix = "x86" in { 101 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". 147 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86." [all...] |