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  /build/target/board/generic_x86/
BoardConfig.mk 9 TARGET_CPU_ABI := x86
10 TARGET_ARCH := x86
11 TARGET_ARCH_VARIANT := x86-atom
  /external/llvm/test/CodeGen/X86/
2006-10-07-ScalarSSEMiscompile.ll 1 ; RUN: llc < %s -march=x86 -mattr=sse | grep movaps
10 %tmp28 = tail call <4 x float> @llvm.x86.sse.sub.ss( <4 x float> %A, <4 x float> %BV ) ; <<4 x float>> [#uses=1]
14 declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>)
2007-06-28-X86-64-isel.ll 1 ; RUN: llc < %s -march=x86-64 -mattr=+sse2
4 %tmp1 = call <8 x i16> @llvm.x86.sse2.pmins.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 7, i32 7, i32 7, i32 7 > to <8 x i16>) )
16 declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>)
2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll 1 ; RUN: llc < %s -tailcallopt -march=x86-64 -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep fstpt
2 ; RUN: llc < %s -tailcallopt -march=x86-64 -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep xmm
4 ; Check that x86-64 tail calls support x86_fp80 and v2f32 types. (Tail call
shl_elim.ll 1 ; RUN: llc < %s -march=x86 | grep {movl 8(.esp), %eax}
2 ; RUN: llc < %s -march=x86 | grep {shrl .eax}
3 ; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax}
xmm-r64.ll 1 ; RUN: llc < %s -march=x86-64
4 %tmp1039 = call <4 x i32> @llvm.x86.sse2.psll.d( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>> [#uses=1]
11 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>)
sse_reload_fold.ll 12 declare <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float>)
13 declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>)
14 declare <4 x float> @llvm.x86.sse.rcp.ps(<4 x float>)
15 declare <4 x float> @llvm.x86.sse.min.ps(<4 x float>, <4 x float>)
16 declare <4 x float> @llvm.x86.sse.max.ps(<4 x float>, <4 x float>)
17 declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8)
18 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)
19 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>)
20 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
21 declare <2 x double> @llvm.x86.sse2.sqrt.pd(<2 x double>
    [all...]
sse42.ll 4 declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
5 declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
6 declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind
9 %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)
20 %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)
31 %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)
2006-05-22-FPSetEQ.ll 1 ; RUN: llc < %s -march=x86 -mattr=-sse | grep setnp
2 ; RUN: llc < %s -march=x86 -mattr=-sse -enable-unsafe-fp-math -enable-no-nans-fp-math | \
atomic-load-store-wide.ll 1 ; RUN: llc < %s -march=x86 | FileCheck %s
3 ; 64-bit load/store on x86-32
fast-cc-callee-pops.ll 1 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=yonah | FileCheck %s
fast-isel-tailcall.ll 1 ; RUN: llc < %s -fast-isel -tailcallopt -march=x86 | not grep add
4 ; On x86, -tailcallopt changes the ABI so the caller shouldn't readjust
mmx-insert-element.ll 1 ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | grep movq
2 ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | grep pshufd
mul-shift-reassoc.ll 1 ; RUN: llc < %s -march=x86 | grep lea
2 ; RUN: llc < %s -march=x86 | not grep add
sse-load-ret.ll 1 ; RUN: llc < %s -march=x86 -mcpu=yonah | not grep movss
2 ; RUN: llc < %s -march=x86 -mcpu=yonah | not grep xmm
store-fp-constant.ll 1 ; RUN: llc < %s -march=x86 | not grep rodata
2 ; RUN: llc < %s -march=x86 | not grep literal
tls1.ll 1 ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
3 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
tls10.ll 1 ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
4 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
tls11.ll 1 ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
3 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
tls12.ll 1 ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
3 ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
  /external/clang/test/CodeGen/
avx-cmp-builtins.c 14 // CHECK: @llvm.x86.sse2.cmp.pd({{.*}}, i8 13)
20 // CHECK: @llvm.x86.sse.cmp.ps({{.*}}, i8 13)
26 // CHECK: @llvm.x86.avx.cmp.pd.256({{.*}}, i8 13)
32 // CHECK: @llvm.x86.avx.cmp.ps.256({{.*}}, i8 13)
38 // CHECK: @llvm.x86.sse2.cmp.sd({{.*}}, i8 13)
44 // CHECK: @llvm.x86.sse.cmp.ss({{.*}}, i8 13)
  /external/libffi/
Libffi.mk 29 ifeq ($(ffi_os)-$(ffi_arch),linux-x86)
30 LOCAL_SRC_FILES := src/x86/ffi.c src/x86/sysv.S
37 ifeq ($(ffi_os)-$(ffi_arch),darwin-x86)
38 LOCAL_SRC_FILES := src/x86/ffi.c src/x86/darwin.S
Makefile.am 27 src/sparc/ffi.c src/x86/darwin64.S \
28 src/x86/ffi.c src/x86/sysv.S src/x86/win32.S src/x86/darwin.S \
29 src/x86/freebsd.S \
30 src/x86/ffi64.c src/x86/unix64.S src/x86/ffitarget.h \
96 if X86
    [all...]
  /external/clang/test/CodeGenObjC/
try.m 1 // REQUIRES: x86-registered-target,x86-64-registered-target
  /external/llvm/lib/Target/X86/
X86ELFWriterInfo.cpp 1 //===-- X86ELFWriterInfo.cpp - ELF Writer Info for the X86 backend --------===//
10 // This file implements ELF writer information for the X86 backend.
38 case X86::reloc_pcrel_word:
40 case X86::reloc_absolute_word:
42 case X86::reloc_absolute_word_sext:
44 case X86::reloc_absolute_dword:
46 case X86::reloc_picrel_word:
52 case X86::reloc_pcrel_word:
54 case X86::reloc_absolute_word:
56 case X86::reloc_absolute_word_sext
    [all...]

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