| /external/oprofile/events/mips/34K/ |
| events | 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
72 event:0x31 counters:0 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
96 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
98 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
99 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
100 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misse
[all...] |
| /external/webkit/LayoutTests/dom/xhtml/level3/core/ |
| nodesettextcontent08.js | 80 Using setTextContent on a new Processing Instruction node, attempt to set its data to PID.
|
| nodeinsertbefore01.js | 83 attempt to insert a new Processing Instruction node before the new Comment and
|
| nodeinsertbefore02.js | 80 attempt to insert a new Processing Instruction node before the new Comment and
|
| /external/llvm/lib/Transforms/IPO/ |
| DeadArgumentElimination.cpp | 228 Instruction *Call = CS.getInstruction();
244 Instruction *New;
373 /// return instruction. This is used in the recursion, you should always leave
381 // that U is really a use of an insertvalue instruction that uses the
416 // label type (for the invoke instruction).
507 const Instruction *TheCall = CS.getInstruction();
781 Instruction *Call = CS.getInstruction();
822 Instruction *New;
853 Instruction *InsertPt = Call
[all...] |
| MergeFunctions.cpp | 18 // iterates through each instruction in each basic block.
175 /// Instruction::isSameOperationAs but with modifications to the type
177 bool isEquivalentOperation(const Instruction *I1,
178 const Instruction *I2) const;
285 // Instruction::isSameOperationAs.
286 bool FunctionComparator::isEquivalentOperation(const Instruction *I1,
287 const Instruction *I2) const {
288 // Differences from Instruction::isSameOperationAs:
797 // to call it and hope that we improve the instruction cache hit rate.
849 // For each instruction used by the value, remove() the function that contain
[all...] |
| ArgumentPromotion.cpp | 73 /// A vector used to hold the indices of a single GEP instruction
511 // OriginalLoads - Keep track of a representative load instruction from the
554 Instruction *User = cast<Instruction>(*UI);
644 Instruction *Call = CS.getInstruction();
732 Instruction *New;
[all...] |
| /external/llvm/lib/CodeGen/ |
| IntrinsicLowering.cpp | 165 /// instruction IP.
166 static Value *LowerBSWAP(LLVMContext &Context, Value *V, Instruction *IP) {
261 /// instruction IP.
262 static Value *LowerCTPOP(LLVMContext &Context, Value *V, Instruction *IP) {
301 /// instruction IP.
302 static Value *LowerCTLZ(LLVMContext &Context, Value *V, Instruction *IP) {
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 41 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
43 /// switch or atomic instruction, which may expand to multiple basic blocks.
44 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
51 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
75 // instruction values that are used outside of the block that defines
380 assert(CE->getOpcode() == Instruction::BitCast &&
457 /// landingpad instruction and add them to the specified machine module info.
|
| /external/oprofile/events/mips/74K/ |
| events | 22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
27 event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer
38 event:0x14 counters:0,2 um:zero minimum:500 name:SINGLE_ISSUE_CYCLES : 20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles
39 event:0x15 counters:0,2 um:zero minimum:500 name:OOO_ALU_ISSUE_CYCLES : 21-0 Out-of-order ALU issue cycles (issued instruction is not the oldest in the pool)
43 event:0x19 counters:0,2 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 25-0 Joint TLB data (non-instruction) accesses
52 event:0x23 counters:0,2 um:zero minimum:500 name:LOAD_MISS_CONSUMER_REPLAYS : 35-0 Replays following optimistic issue of instruction dependent on load which missed, counted only when the dependent instruction graduate
[all...] |
| /external/proguard/src/proguard/classfile/editor/ |
| CodeAttributeComposer.java | 28 import proguard.classfile.instruction.*;
29 import proguard.classfile.instruction.visitor.InstructionVisitor;
161 * Appends the given instruction with the given old offset.
162 * @param oldInstructionOffset the old offset of the instruction, to which
165 * @param instruction the instruction to be appended.
168 Instruction instruction)
172 println("["+codeLength+"] <- ", instruction.toString(oldInstructionOffset));
176 int newCodeLength = codeLength + instruction.length(codeLength)
276 Instruction instruction = InstructionFactory.create(code, instructionOffset); local
[all...] |
| ConstantPoolRemapper.java | 32 import proguard.classfile.instruction.*;
33 import proguard.classfile.instruction.visitor.InstructionVisitor;
451 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
460 // Replace the instruction.
461 Instruction replacementInstruction =
|
| /external/llvm/lib/Analysis/ |
| DIBuilder.cpp | [all...] |
| PathNumbering.cpp | 379 Instruction& instr = *bbCurrent;
380 if( instr.getOpcode() == Instruction::Call ) {
|
| /external/llvm/tools/bugpoint/ |
| ExtractFunction.cpp | 53 /// deletes the specified instruction from the cloned module. It then runs a
57 Module *BugDriver::deleteInstructionFromProgram(const Instruction *I,
74 Instruction *TheInst = RI; // Got the corresponding instruction!
76 // If this instruction produces a value, replace any users with null values
80 // Remove the instruction from the program.
96 errs() << "Instruction removal failed. Sorry. :( Please report a bug!\n";
|
| /external/oprofile/events/mips/1004K/ |
| events | 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
73 event:0x31 counters:0 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
104 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
106 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
107 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
108 event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misse
[all...] |
| /external/oprofile/events/mips/r10000/ |
| events | 23 event:0x09 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
25 event:0x0a counters:0 um:zero minimum:500 name:SCACHE_MISSES_INSTRUCTION : Secondary cache misses (instruction)
27 event:0x0b counters:0 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTED_INSN : Secondary cache way mispredicted (instruction)
|
| /external/oprofile/events/mips/r12000/ |
| events | 13 event:0x9 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
14 event:0xa counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_SECONDARY_CACHE_MISSES : Secondary cache misses (instruction)
15 event:0xb counters:0,1,2,3 um:zero minimum:500 name:SECONDARY_CACHE_WAY_MISSPREDICTED : Secondary cache way mispredicted (instruction)
|
| /external/oprofile/events/mips/rm9000/ |
| events | 10 event:0x06 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_DUAL_ISSUED : Dual-issued instruction pairs
17 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
18 event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
|
| /external/proguard/src/proguard/optimize/peephole/ |
| MethodInliner.java | 29 import proguard.classfile.instruction.*;
30 import proguard.classfile.instruction.visitor.InstructionVisitor;
320 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
322 codeAttributeComposer.appendInstruction(offset, instruction.shrink());
328 // Are we inlining this instruction?
340 // Are we not at the last instruction?
343 // Replace the return instruction by a branch instruction.
344 Instruction branchInstruction
[all...] |
| /external/llvm/examples/ParallelJIT/ |
| ParallelJIT.cpp | 55 // Create the add instruction, inserting it into the end of BB.
56 Instruction *Add = BinaryOperator::CreateAdd(One, ArgX, "addresult", BB);
58 // Create the return instruction and add it to the basic block
109 // Create the return instruction and add it to the basic block
|
| /external/llvm/include/llvm/Analysis/ |
| RegionInfo.h | 372 /// @brief Check if the region contains an Instruction.
374 /// @param Inst The Instruction that might be contained in this region.
375 /// @return True if the Instruction is contained in the region otherwise false.
376 bool contains(const Instruction *Inst) const {
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGISel.h | 11 // base class for SelectionDAG-based instruction selectors.
40 /// pattern-matching instruction selectors.
68 /// instruction selection starts.
81 /// (which will appear in the machine instruction) should be added to the
90 /// operand node N of U during instruction selection that starts at Root.
94 /// U can be folded during instruction selection that starts at Root.
169 /// DAGSize - Size of DAG being instruction selected.
174 /// instruction selection as it procedes through the topologically-sorted
180 /// instruction selection graph.
283 bool TryToFoldFastISelLoad(const LoadInst *LI, const Instruction *FoldInst
[all...] |
| /external/llvm/lib/Analysis/IPA/ |
| CallGraph.cpp | 134 || !CallSite(cast<Instruction>(U)).isCallee(I)) {
|
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.h | 137 SmallVector<Instruction *, 64> InstructionList;
|
