| /frameworks/base/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Dot_p_neon.s | 117 SUB r10, r10, #1 @ sft = norm_l(L_sum)
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_Align_unsafe_s.s | 227 SUB pSrc, pDst, #28
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_Align_unsafe_s.s | 227 SUB pSrc, pDst, #28
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_DequantTransformResidualFromPairAndAdd_s.S | 18 SUB sp,sp,#0x20
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/source/arm11_asm/ |
| h264bsd_interpolate_hor_ver_quarter.s | 96 SUB sp, sp, #0x1e4
160 SUB partW, partW, #1;
161 SUB partH, partH, #1;
516 SUB ref, ref, width, LSL #3 ;// ref -= 8*width;
|
| /packages/apps/Calculator/ |
| arity-2.1.2.jar | |
| /external/v8/src/ia32/ |
| code-stubs-ia32.cc | 519 case Token::SUB:
616 case Token::SUB:
617 __ sub(left, Operand(right));
687 case Token::SUB:
717 __ sub(right, Operand(left));
719 case Token::SUB:
763 case Token::SUB:
772 __ sub(right, Operand(left));
774 case Token::SUB:
797 case Token::SUB: __ subsd(xmm0, xmm1); break
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| GGLAssembler.cpp | 321 SUB(AL, S, parts.count.reg, parts.count.reg, imm(1<<16));
338 SUB(AL, S, parts.count.reg, parts.count.reg, imm(1<<16));
364 SUB(AL, 0, parts.count.reg, parts.count.reg, Rx);
365 SUB(AL, 0, parts.count.reg, parts.count.reg, imm(1));
766 SUB(AL, 0, zbase, zbase, reg_imm(parts.count.reg, LSR, 15));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 447 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
469 if (N.getOpcode() == ISD::SUB)
502 AddSub = ARM_AM::sub;
517 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
531 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
557 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
602 AddSub = ARM_AM::sub;
617 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
637 if (N.getOpcode() != ISD::SUB) {
[all...] |
| /dalvik/dx/src/com/android/dx/cf/code/ |
| RopperMachine.java | 539 if (rop.getOpcode() == RegOps.SUB) {
796 return RegOps.SUB;
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| SCCP.java | 409 case RegOps.SUB:
410 // 1 source for reverse sub, 2 sources for regular sub
510 case RegOps.SUB:
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| omxVCM4P2_MCReconBlock_s.s | 466 SUB yMask, yMask, #2
670 SUB dstStep, dstStep, #4
|
| /external/v8/src/arm/ |
| constants-arm.h | 194 SUB = 2 << 21, // Subtract.
|
| /external/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 547 @ SUB (immediate)
559 @ SUB (SP minus immediate)
561 sub sp, #12
562 sub sp, sp, #508
564 @ CHECK: sub sp, #12 @ encoding: [0x83,0xb0]
565 @ CHECK: sub sp, #508 @ encoding: [0xff,0xb0]
569 @ SUB (register)
|
| /external/v8/src/ |
| ast.cc | 156 case Token::ASSIGN_SUB: return Token::SUB;
307 case Token::SUB:
328 case Token::SUB:
|
| /external/webkit/Source/JavaScriptCore/assembler/ |
| ARMAssembler.h | 127 SUB = (0x2 << 21),
303 emitInst(static_cast<ARMWord>(cc) | SUB, rd, rn, op2);
308 emitInst(static_cast<ARMWord>(cc) | SUB | SET_CC, rd, rn, op2);
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_IDCT_s.h | 438 SUB pSrc, pDest, #(64*2)
496 SUB pSrc, pDest, #(64*2)
[all...] |
| armCOMM_s.h | 488 SUB $_base, $_base, $_offset
649 _M_OPC SUB, sp, sp, _SBytes
827 SUB sp, sp, #16
|
| /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_IDCT_s.h | 444 SUB pSrc, pDest, #(64*2)
502 SUB pSrc, pDest, #(64*2)
[all...] |
| armCOMM_s.h | 491 SUB $_base, $_base, $_offset
652 _M_OPC SUB, sp, sp, _SBytes
830 SUB sp, sp, #16
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 280 setOperationAction(ISD::SUB, MVT::i8, Custom);
281 setOperationAction(ISD::SUB, MVT::i64, Legal);
408 // add/sub are legal for all supported vector VT's.
410 setOperationAction(ISD::SUB, VT, Legal);
716 DAG.getNode(ISD::SUB, dl, MVT::i32,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 105 case ISD::SUB:
141 // If the result is null then the sub-method took care of registering it.
317 return DAG.getNode(ISD::SUB, dl, NVT, Op,
457 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
620 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 99 setOperationAction(ISD::SUB, MVT::i64, Custom);
183 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
203 case ISD::SUB:
708 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
[all...] |
| /external/webkit/Source/WebCore/rendering/ |
| RenderTableSection.cpp | 403 if (va == BASELINE || va == TEXT_BOTTOM || va == TEXT_TOP || va == SUPER || va == SUB) {
656 if (va == BASELINE || va == TEXT_BOTTOM || va == TEXT_TOP || va == SUPER || va == SUB) {
669 case SUB:
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 557 SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
594 SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
600 SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64,
687 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1);
[all...] |
