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  /external/openssl/crypto/
ppccpuid.pl 42 xor r10,r10,r10
x86_64cpuid.pl 86 movzb %cl,%r10 # number of cores - 1
87 inc %r10 # number of cores
204 xorq %r10,%r10
225 xorq %r10,%r10
  /external/valgrind/main/coregrind/m_syswrap/
syscall-amd64-linux.S 118 movq %r8, %r10 // sigsetSzB
135 movq OFFSET_amd64_R10(%rax), %r10
160 movq %r8, %r10 // sigsetSzB
  /external/libvpx/vp8/encoder/ppc/
sad_altivec.asm 34 li r10, 16 ;# load offset and loop counter
61 lvx v2, r10, r5
77 lvx v2, r10, r5
95 lvx v2, r10, r5
116 load_aligned_16 v4, r3, r10
117 load_aligned_16 v5, r5, r10
124 load_aligned_16 v6, r3, r10
125 load_aligned_16 v7, r5, r10
rdopt_altivec.asm 29 li r10, 16
37 lvx v0, r10, r3 ;# Coeff
38 lvx v1, r10, r4 ;# dqcoeff
  /frameworks/base/media/libstagefright/codecs/aacenc/src/asm/ARMV5E/
CalcWindowEnergy_v5.s 33 ldr r10, [r0, #168] @ states0 = blockSwitchingControl->iirStates[0];
66 sub r0, r3, r10 @ accu3 = accu1 - states0;
69 mov r10, r3 @ states0 = accu1;
100 str r10, [r0, #168]
  /frameworks/base/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/
syn_filt_neon.s 59 MOV r10, r13 @ temp = y_buf
62 VLD1.S16 {D4, D5, D6, D7}, [r10]! @ first 16 temp_p
68 ADD r10, r4, r8, LSL #1 @ y[i], yy[i] address
89 STRH r9, [r10] @ yy[i]
  /system/core/debuggerd/arm/
crashglue.S 17 ldr r10, =0xa5a50010
  /dalvik/vm/mterp/armv5te/
footer.S 22 ldr r10, [rSELF,#offThread_jitResumeNPC] @ resume address
27 @ expects resume addr in r10
355 mov r10, r0 @ save target
357 cmp r0, r10 @ special case?
400 * r10: the address of the target translation.
406 mov r3,r10 @ r3<- target translation
409 bx r10 @ jump to the translation
491 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area
512 SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save are
    [all...]
OP_EXECUTE_INLINE.S 18 FETCH(r10, 1) @ r10<- BBBB
39 * r10 = call index
63 ldr pc, [rINST, r10, lsl #4] @ sizeof=16, "func" is first entry
68 * r10: opIndex
71 mov r0, r10
OP_EXECUTE_INLINE_RANGE.S 16 FETCH(r10, 1) @ r10<- BBBB
37 * r10 = call index
55 ldr pc, [r9, r10, lsl #4] @ sizeof=16, "func" is first entry
61 * r10: opIndex
64 mov r0, r10
entry.S 47 .save {r4-r10,fp,lr}; \
48 stmfd sp!, {r4-r10,fp,lr} @ save 9 regs
123 ldmfd sp!, {r4-r10,fp,pc} @ restore 9 regs and return
  /dalvik/vm/compiler/template/armv5te/
TEMPLATE_CMPL_FLOAT.S 37 mov r10, r1
49 mov r0, r10 @ restore in reverse order
TEMPLATE_STRING_INDEXOF.S 57 * r3, r4, r9, r10, r11, r12 available for loading string data
66 ldrh r10, [r0, #2]!
72 cmp r10, r1
footer.S 19 SAVEAREA_FROM_FP(r10, r1) @ r10<- new stack save area
48 @ native return; r10=newSaveArea
50 ldr r2, [r10, #offStackSaveArea_returnAddr] @ r2 = chaining cell ret
51 ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved->top
56 ldr r0, [r10, #offStackSaveArea_savedPc] @ reload rPC
  /external/webkit/PerformanceTests/SunSpider/tests/sunspider-0.9/
bitops-3bit-bits-in-byte.js 21 addr3,r3,r10
  /external/webkit/PerformanceTests/SunSpider/tests/sunspider-0.9.1/
bitops-3bit-bits-in-byte.js 21 addr3,r3,r10
  /frameworks/base/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/
omxVCM4P10_TransformDequantChromaDCFromPair_s.S 16 push {r4-r10, lr}
51 pop {r4-r10, pc}
  /external/flac/libFLAC/ppc/as/
lpc_asm.s 84 li r10,-4
86 lvewx v0,r10,r9
100 add r10,r5,r6
115 cmplw cr0,r5,r10
129 cmplw cr0,r5,r10
143 cmplw cr0,r5,r10
157 cmplw cr0,r5,r10
171 cmplw cr0,r5,r10
185 cmplw cr0,r5,r10
199 cmplw cr0,r5,r10
    [all...]
  /external/flac/libFLAC/ppc/gas/
lpc_asm.s 86 li r10,-4
88 lvewx v0,r10,r9
102 add r10,r5,r6
117 cmplw cr0,r5,r10
131 cmplw cr0,r5,r10
145 cmplw cr0,r5,r10
159 cmplw cr0,r5,r10
173 cmplw cr0,r5,r10
187 cmplw cr0,r5,r10
201 cmplw cr0,r5,r10
    [all...]
  /external/libvpx/vp8/common/ppc/
copy_altivec.asm 27 li r10, 16
28 mtctr r10
34 lvx v2, r10, r3
  /external/libvpx/vp8/encoder/arm/armv6/
vp8_variance16x16_armv6.asm 54 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
60 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
78 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
84 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
102 uxtb16 r10, r6, ror #8 ; another two pixels to halfwords
108 smlad r11, r10, r10, r11 ; dual signed multiply, add and accumulate (2)
128 uxtb16 r10, r6, ror #8 ; another two pixels to halfword
    [all...]
  /external/valgrind/main/coregrind/m_dispatch/
dispatch-amd64-darwin.S 69 pushq %r10
139 movq 0(%rcx,%rbx,1), %r10 /* .guest */
141 cmpq %rax, %r10
177 movq 0(%rcx,%rbx,1), %r10 /* .guest */
179 cmpq %rax, %r10
270 popq %r10
dispatch-amd64-linux.S 70 pushq %r10
143 movq 0(%rcx,%rbx,1), %r10 /* .guest */
145 cmpq %rax, %r10
184 movq 0(%rcx,%rbx,1), %r10 /* .guest */
186 cmpq %rax, %r10
277 popq %r10
  /frameworks/base/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/
Filt_6k_7k_opt.s 46 LDR r10, Lable1 @ get fir_7k address
84 @ not use registers: r4, r10, r12, r14, r5
88 LDR r0, [r10]
103 LDR r0, [r10, #4]
116 LDR r0, [r10, #8]
123 LDR r0, [r10, #12]
130 LDR r0, [r10, #16]
142 LDR r0, [r10, #20]
150 LDR r0, [r10, #24]
157 LDR r0, [r10, #28]
    [all...]

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1 2 3 4 56 7 8 91011>>