| /external/llvm/lib/Target/X86/ |
| X86InstrCMovSetCC.td | 1 //===- X86InstrCMovSetCC.td - Conditional Move and SetCC ---*- tablegen -*-===//
16 // SetCC instructions.
76 // SetCC instructions.
77 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
88 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
89 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
90 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
91 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
92 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
93 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal t
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-arm.cc | 111 COMPARE(and_(r2, r3, Operand(r4), SetCC),
118 COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
122 COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
127 COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
131 COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
138 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
147 COMPARE(add(r7, r8, Operand(ip), SetCC),
149 COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
156 COMPARE(adc(r5, sp, Operand(ip), SetCC),
158 COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc)
[all...] |
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| exit_compare_live_range.ll | 2 ; having overlapping live ranges that result in copies. We want the setcc
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrFPU.td | 140 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
146 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOEQ),
149 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
153 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETONE),
157 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGT),
160 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLT),
163 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
166 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETLE),
169 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGT)
[all...] |
| MBlazeInstrInfo.td | 754 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
757 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
760 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGT),
763 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLT),
766 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE),
769 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETLE),
772 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
775 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
778 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGE),
781 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE)
[all...] |
| MBlazeISelLowering.h | 104 /// getSetCCResultType - get the ISD::SETCC result ValueType
|
| /external/llvm/lib/Target/Blackfin/ |
| README.txt | 4 ** DONE Problem with asymmetric SETCC operations
19 possible to represent the setcc instruction without having i1 as a legal type.
96 ** Create test case for each Illegal SETCC case
97 The DAG combiner may someimes produce illegal i16 SETCC instructions.
99 *** TODO SETCC (ctlz x), 5) == const
100 *** TODO SETCC (and load, const) == const
101 *** DONE SETCC (zext x) == const
102 *** TODO SETCC (sext x) == const
|
| /external/llvm/test/CodeGen/Blackfin/ |
| promote-setcc.ll | 3 ; The DAG combiner may sometimes create illegal i16 SETCC operations when run
|
| /external/llvm/test/Transforms/ConstProp/ |
| 2002-09-03-SetCC-Bools.ll | 0 ; SetCC on boolean values was not implemented!
|
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
395 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
[all...] |
| /external/icu4c/tools/gennorm2/ |
| n2builder.h | 59 void setCC(UChar32 c, uint8_t cc);
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.td | 282 [(set RegPred:$p, (setcc RC:$a, RC:$b, cmp))]>;
286 [(set RegPred:$p, (setcc RC:$a, imm:$b, cmp))]>;
292 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
297 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp),
303 [(set RegPred:$p, (or (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
308 [(set RegPred:$p, (or (setcc RC:$a, imm:$b, cmp), RegPred:$c))]>;
313 [(set RegPred:$p, (xor (setcc RC:$a, RC:$b, cmp), RegPred:$c))]>;
318 [(set RegPred:$p, (xor (setcc RC:$a, imm:$b, cmp),
325 [(set RegPred:$p, (and (setcc RC:$a, RC:$b, cmp),
331 [(set RegPred:$p, (and (setcc RC:$a, imm:$b, cmp)
[all...] |
| PTXISelLowering.cpp | 75 // select_cc => setcc
92 // customise setcc to use bitwise logic if possible
94 setOperationAction(ISD::SETCC, MVT::i1, Custom);
113 case ISD::SETCC:
148 assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2004-11-27-SetCCForCastLargerAndConstant.ll | 8 ; cast operands, and types of setCC operators. In all cases, the cast should
9 ; be eliminated. In many cases the setCC is also eliminated based on the
|
| /external/llvm/lib/Target/CellSPU/ |
| SPU64InstrInfo.td | 18 // 3. i64 setcc results are i32, which are subsequently converted to a FSM
21 // 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
48 // setcc the negative condition:
64 // i64 seteq (equality): the setcc result is i32, which is converted to a
67 // v2i64 seteq (equality): the setcc result is v4i32
|
| SPUISelLowering.h | 109 /// getSetCCResultType - Return the ValueType for ISD::SETCC
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 495 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
496 // that selects between the values 1 and 0, making it equivalent to a setcc.
502 if (N.getOpcode() == ISD::SETCC) {
521 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| LegalizeFloatTypes.cpp | 591 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
611 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
618 assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
675 default: assert(false && "Do not know how to soften this setcc!");
686 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT),
689 NewLHS = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(RetVT), NewLHS,
[all...] |
| /external/llvm/include/llvm/Transforms/Utils/ |
| Local.h | 130 /// FoldBranchToCommonDest - If this basic block is ONLY a setcc and a branch,
132 /// setcc into the predecessor and use logical operations to pick the right
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.h | 68 /// getSetCCResultType - Get the SETCC result ValueType
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 328 // Much like the scalar select and setcc, each bit in the condition selects
338 // SetCC operator - This evaluates to a true value iff the condition is
344 SETCC,
492 // compare, rather than as a combined SetCC node. The operands in order are
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 731 // Sparc has no select or setcc: expand to SELECT_CC.
735 setOperationAction(ISD::SETCC, MVT::i32, Expand);
736 setOperationAction(ISD::SETCC, MVT::f32, Expand);
737 setOperationAction(ISD::SETCC, MVT::f64, Expand);
[all...] |
| /external/v8/src/arm/ |
| code-stubs-arm.cc | 321 __ and_(exponent, source_, Operand(HeapNumber::kSignMask), SetCC);
695 __ and_(dst2, scratch1, Operand(HeapNumber::kSignMask), SetCC);
697 __ rsb(scratch1, scratch1, Operand(0), SetCC, mi);
716 __ sub(scratch2, dst1, Operand(HeapNumber::kMantissaBitsInTopWord), SetCC);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 573 /// associated with the SetCC condition, and whether or not the field is
617 // We can codegen setcc op, imm very efficiently compared to a brcond.
619 // setcc op, 0
649 } else if (Imm == ~0U) { // setcc op, -1
819 case ISD::SETCC:
[all...] |
