Lines Matching full:outw
74 outw(RX_DISABLE, BASE + VX_COMMAND);
75 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
77 outw(TX_DISABLE, BASE + VX_COMMAND);
78 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
80 outw(RX_RESET, BASE + VX_COMMAND);
82 outw(TX_RESET, BASE + VX_COMMAND);
84 outw(C_INTR_LATCH, BASE + VX_COMMAND);
85 outw(SET_RD_0_MASK, BASE + VX_COMMAND);
86 outw(SET_INTR_MASK, BASE + VX_COMMAND);
87 outw(SET_RX_FILTER, BASE + VX_COMMAND);
97 /* outw(0, BASE + VX_W0_CONFIG_CTRL); */
100 /* outw(SET_IRQ(0), BASE + VX_W0_RESOURCE_CFG); */
103 /* outw(ENABLE_DRQ_IRQ, BASE + VX_W0_CONFIG_CTRL); */
111 outw(RX_RESET, BASE + VX_COMMAND);
113 outw(TX_RESET, BASE + VX_COMMAND);
121 outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
123 outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE |
133 outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
135 outw(SET_RX_FILTER | FIL_INDIVIDUAL |
146 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
151 outw(RX_ENABLE, BASE + VX_COMMAND);
152 outw(TX_ENABLE, BASE + VX_COMMAND);
195 outw(TX_RESET, BASE + VX_COMMAND);
196 outw(TX_ENABLE, BASE + VX_COMMAND);
206 outw(len, BASE + VX_W1_TX_PIO_WR_1);
207 outw(0x0, BASE + VX_W1_TX_PIO_WR_1); /* Second dword meaningless */
212 outw(t, BASE + VX_W1_TX_PIO_WR_1);
245 outw(ACK_INTR | cst, BASE + VX_COMMAND);
246 outw(C_INTR_LATCH, BASE + VX_COMMAND);
257 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
300 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
343 outw(EEPROM_CMD_RD | offset, BASE + VX_W0_EEPROM_COMMAND);
415 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
418 outw(0, BASE + VX_W4_MEDIA_TYPE);
424 outw(ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
427 outw(START_TRANSCEIVER,BASE + VX_COMMAND);
433 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
443 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
446 outw(0, BASE + VX_W4_MEDIA_TYPE);
464 outw(GLOBAL_RESET, BASE + VX_COMMAND);
484 outw(ntohs(p[i]), BASE + VX_W2_ADDR_0 + (i * 2));
