Lines Matching refs:BASE
74 outw(RX_DISABLE, BASE + VX_COMMAND);
75 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
77 outw(TX_DISABLE, BASE + VX_COMMAND);
78 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
80 outw(RX_RESET, BASE + VX_COMMAND);
82 outw(TX_RESET, BASE + VX_COMMAND);
84 outw(C_INTR_LATCH, BASE + VX_COMMAND);
85 outw(SET_RD_0_MASK, BASE + VX_COMMAND);
86 outw(SET_INTR_MASK, BASE + VX_COMMAND);
87 outw(SET_RX_FILTER, BASE + VX_COMMAND);
97 /* outw(0, BASE + VX_W0_CONFIG_CTRL); */
100 /* outw(SET_IRQ(0), BASE + VX_W0_RESOURCE_CFG); */
103 /* outw(ENABLE_DRQ_IRQ, BASE + VX_W0_CONFIG_CTRL); */
109 outb(nic->node_addr[i], BASE + VX_W2_ADDR_0 + i);
111 outw(RX_RESET, BASE + VX_COMMAND);
113 outw(TX_RESET, BASE + VX_COMMAND);
119 inb(BASE + VX_W1_TX_STATUS);
122 S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
124 S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
133 outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
136 FIL_BRDCST, BASE + VX_COMMAND);
143 j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK;
144 outl(BASE + VX_W3_INTERNAL_CFG, j | (i <<INTERNAL_CONNECTOR_BITS));
146 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
151 outw(RX_ENABLE, BASE + VX_COMMAND);
152 outw(TX_ENABLE, BASE + VX_COMMAND);
193 while(( status=inb(BASE + VX_W1_TX_STATUS) )& TXS_COMPLETE ) {
195 outw(TX_RESET, BASE + VX_COMMAND);
196 outw(TX_ENABLE, BASE + VX_COMMAND);
199 outb(0x0, BASE + VX_W1_TX_STATUS);
202 while (inw(BASE + VX_W1_FREE_TX) < len + pad + 4) {
206 outw(len, BASE + VX_W1_TX_PIO_WR_1);
207 outw(0x0, BASE + VX_W1_TX_PIO_WR_1); /* Second dword meaningless */
210 outsw(BASE + VX_W1_TX_PIO_WR_1, d, ETH_ALEN/2);
211 outsw(BASE + VX_W1_TX_PIO_WR_1, nic->node_addr, ETH_ALEN/2);
212 outw(t, BASE + VX_W1_TX_PIO_WR_1);
213 outsw(BASE + VX_W1_TX_PIO_WR_1, p, s / 2);
215 outb(*(p+s - 1), BASE + VX_W1_TX_PIO_WR_1);
218 outb(0, BASE + VX_W1_TX_PIO_WR_1); /* Padding */
221 while((inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) != 0)
236 cst=inw(BASE + VX_STATUS);
245 outw(ACK_INTR | cst, BASE + VX_COMMAND);
246 outw(C_INTR_LATCH, BASE + VX_COMMAND);
251 status = inw(BASE + VX_W1_RX_STATUS);
257 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
269 insw(BASE + VX_W1_RX_PIO_RD_1, nic->packet, rx_fifo / 2);
271 nic->packet[rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1);
275 status = inw(BASE + VX_W1_RX_STATUS);
282 insw(BASE + VX_W1_RX_PIO_RD_1, nic->packet+nic->packetlen, rx_fifo / 2);
284 nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1);
300 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
301 while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS);
323 for (i = 0; is_eeprom_busy(BASE) && i < MAX_EEPROMBUSY; i++)
343 outw(EEPROM_CMD_RD | offset, BASE + VX_W0_EEPROM_COMMAND);
346 return (inw(BASE + VX_W0_EEPROM_DATA));
355 vx_connectors = inw(BASE + VX_W3_RESET_OPT) & 0x7f;
370 vx_connector = (inl(BASE + VX_W3_INTERNAL_CFG)
411 j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK;
412 outl(j | (i <<INTERNAL_CONNECTOR_BITS), BASE + VX_W3_INTERNAL_CFG);
415 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
418 outw(0, BASE + VX_W4_MEDIA_TYPE);
424 outw(ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
427 outw(START_TRANSCEIVER,BASE + VX_COMMAND);
433 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
443 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
446 outw(0, BASE + VX_W4_MEDIA_TYPE);
464 outw(GLOBAL_RESET, BASE + VX_COMMAND);
484 outw(ntohs(p[i]), BASE + VX_W2_ADDR_0 + (i * 2));
