Lines Matching refs:Reg
117 SibValueInfo(unsigned Reg, VNInfo *VNI)
119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
158 bool isRegToSpill(unsigned Reg) {
160 RegsToSpill.end(), Reg) != RegsToSpill.end();
163 bool isSibling(unsigned Reg);
175 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
184 void spillAroundUses(unsigned Reg);
209 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
211 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
214 if (MI->getOperand(0).getReg() == Reg)
216 if (MI->getOperand(1).getReg() == Reg)
225 unsigned Reg = Edit->getReg();
228 // besides copies to/from Reg or spills/fills. We accept:
230 // %snip = COPY %Reg / FILL fi#
232 // %Reg = COPY %snip / SPILL %snip, fi#
241 RI = MRI.reg_nodbg_begin(SnipLI.reg);
244 // Allow copies to/from Reg.
245 if (isFullCopyOf(MI, Reg))
250 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
254 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
268 unsigned Reg = Edit->getReg();
271 RegsToSpill.assign(1, Reg);
276 if (Original == Reg)
279 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
281 unsigned SnipReg = isFullCopyOf(MI, Reg);
309 bool InlineSpiller::isSibling(unsigned Reg) {
310 return TargetRegisterInfo::isVirtualRegister(Reg) &&
311 VRM.getOriginal(Reg) == Original;
490 // List of (Reg, VNI) that have been inserted into SibValues, but need to be
496 unsigned Reg;
498 tie(Reg, VNI) = WorkList.pop_back_val();
499 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
528 LiveInterval &LI = LIS.getInterval(Reg);
551 SibValues.insert(std::make_pair(PHIs[i], SibValueInfo(Reg, PHIs[i])));
558 SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI)));
564 WorkList.push_back(std::make_pair(Reg, NonPHI));
578 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
605 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
639 unsigned Reg = RegsToSpill[i];
640 LiveInterval &LI = LIS.getInterval(Reg);
652 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
657 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
738 /// redundant spills of this value in SLI.reg and sibling copies.
748 unsigned Reg = LI->reg;
753 if (isRegToSpill(Reg))
761 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
770 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
783 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
826 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
843 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
864 // If the instruction also writes VirtReg.reg, it had better not require the
868 tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops);
874 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
894 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
902 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
903 MO.setReg(NewLI.reg);
928 unsigned Reg = RegsToSpill[i];
929 LiveInterval &LI = LIS.getInterval(Reg);
931 RI = MRI.use_nodbg_begin(Reg);
940 unsigned Reg = RegsToSpill[i];
941 LiveInterval &LI = LIS.getInterval(Reg);
948 MI->addRegisterDead(Reg, &TRI);
965 unsigned Reg = RegsToSpill[i-1];
966 if (!LIS.hasInterval(Reg)) {
970 LiveInterval &LI = LIS.getInterval(Reg);
973 Edit->eraseVirtReg(Reg, LIS);
985 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
993 if (InstrReg != Reg || FI != StackSlot)
1058 /// insertReload - Insert a reload of NewLI.reg before MI.
1063 TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
1064 MRI.getRegClass(NewLI.reg), &TRI);
1075 /// insertSpill - Insert a spill of NewLI.reg after MI.
1079 TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
1080 MRI.getRegClass(NewLI.reg), &TRI);
1090 /// spillAroundUses - insert spill code around each use of Reg.
1091 void InlineSpiller::spillAroundUses(unsigned Reg) {
1092 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
1093 LiveInterval &OldLI = LIS.getInterval(Reg);
1095 // Iterate over instructions using Reg.
1096 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
1122 if (coalesceStackAccess(MI, Reg))
1128 tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops);
1138 unsigned SibReg = isFullCopyOf(MI, Reg);
1147 // Hoist the spill of a sib-reg copy.
1155 // This is a reload for a sib-reg copy. Drop spills downstream.
1168 LiveInterval &NewLI = Edit->createFrom(Reg, LIS, VRM);
1178 MO.setReg(NewLI.reg);
