Lines Matching defs:Op1
346 unsigned Op1 = getRegForValue(I->getOperand(1));
347 if (Op1 == 0) return false;
351 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
400 unsigned Op1 = getRegForValue(I->getOperand(1));
401 if (Op1 == 0)
411 Op1, Op1IsKill);
1023 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1053 unsigned /*Op1*/, bool /*Op1IsKill*/,
1133 unsigned Op1, bool Op1IsKill) {
1140 .addReg(Op1, Op1IsKill * RegState::Kill);
1144 .addReg(Op1, Op1IsKill * RegState::Kill);
1154 unsigned Op1, bool Op1IsKill,
1162 .addReg(Op1, Op1IsKill * RegState::Kill)
1167 .addReg(Op1, Op1IsKill * RegState::Kill)
1243 unsigned Op1, bool Op1IsKill,
1251 .addReg(Op1, Op1IsKill * RegState::Kill)
1256 .addReg(Op1, Op1IsKill * RegState::Kill)
