Lines Matching full:operand
152 /// getMachineOpValue - Return binary encoding of operand. If the machine
153 /// operand requires relocation, record the relocation and return zero.
162 // operand values, instead querying getMachineOpValue() directly for
163 // each operand it needs to encode. Thus, any of the new encoder
348 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
349 /// machine operand requires relocation, record the relocation and return
427 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
428 /// machine operand requires relocation, record the relocation and return zero.
447 llvm_unreachable("Unsupported operand type for movw/movt");
452 /// getMachineOpValue - Return binary encoding of operand. If the machine
453 /// operand requires relocation, record the relocation and return zero.
1020 // Set shift operand (bit[7:4]).
1035 // Set shift operand (bit[6:4]).
1153 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1157 // Encode first non-shifter register operand if there is one.
1169 // Encode shifter operand.
1217 // Operand 0 of a pre- and post-indexed store is the address base
1225 // Set first operand
1232 // Set second operand
1239 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1288 // Operand 0 of a pre- and post-indexed store is the address base
1296 // Set first operand
1299 // Skip LDRD and STRD's second operand.
1303 // Set second operand
1310 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1375 // Skip operand 0 of an instruction with base register update.
1380 // Set base address operand
1459 // Two register operand form.
1470 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1710 // If this is a two-address operand, skip it, e.g. FMACD.
1721 // FCMPEZD etc. has only one operand.
1839 // Skip operand 0 of an instruction with base register update.
1844 // Set base address operand
1966 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
