Lines Matching refs:SDValue
88 inline SDValue getI32Imm(unsigned Imm) {
96 bool isShifterOpProfitable(const SDValue &Shift,
98 bool SelectRegShifterOperand(SDValue N, SDValue &A,
99 SDValue &B, SDValue &C,
101 bool SelectImmShifterOperand(SDValue N, SDValue &A,
102 SDValue &B, bool CheckProfitability = true);
103 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
104 SDValue &B, SDValue &C) {
108 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
109 SDValue &B) {
114 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
115 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
117 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
118 SDValue &Offset, SDValue &Opc);
119 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
120 SDValue &Opc) {
124 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
125 SDValue &Opc) {
129 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
130 SDValue &Opc) {
137 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
138 SDValue &Offset, SDValue &Opc);
139 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
140 SDValue &Offset, SDValue &Opc);
141 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
142 SDValue &Offset, SDValue &Opc);
143 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
144 bool SelectAddrMode3(SDValue N, SDValue &Base,
145 SDValue &Offset, SDValue &Opc);
146 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
147 SDValue &Offset, SDValue &Opc);
148 bool SelectAddrMode5(SDValue N, SDValue &Base,
149 SDValue &Offset);
150 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
151 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
153 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
156 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
157 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
159 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
160 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
161 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
162 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
163 SDValue &OffImm);
164 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
165 SDValue &OffImm);
166 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
167 SDValue &OffImm);
168 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
169 SDValue &OffImm);
170 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
173 bool SelectT2ShifterOperandReg(SDValue N,
174 SDValue &BaseReg, SDValue &Opc);
175 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
176 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
177 SDValue &OffImm);
178 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
179 SDValue &OffImm);
180 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
181 SDValue &OffReg, SDValue &ShImm);
247 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
248 ARMCC::CondCodes CCVal, SDValue CCR,
249 SDValue InFlag);
250 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
251 ARMCC::CondCodes CCVal, SDValue CCR,
252 SDValue InFlag);
253 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
254 ARMCC::CondCodes CCVal, SDValue CCR,
255 SDValue InFlag);
256 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
257 ARMCC::CondCodes CCVal, SDValue CCR,
258 SDValue InFlag);
269 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
271 std::vector<SDValue> &OutOps);
274 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
275 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
276 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
279 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
280 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
284 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
300 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
316 static bool isScaledConstantInRange(SDValue Node, int Scale,
379 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
390 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
391 SDValue &BaseReg,
392 SDValue &Opc,
413 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
414 SDValue &BaseReg,
415 SDValue &ShReg,
416 SDValue
441 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
442 SDValue &Base,
443 SDValue &OffImm) {
491 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
492 SDValue &Opc) {
589 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
590 SDValue &Base,
591 SDValue &Offset,
592 SDValue &Opc) {
724 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
725 SDValue &Offset, SDValue &Opc) {
760 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
761 SDValue &Offset, SDValue &Opc) {
780 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
781 SDValue &Offset, SDValue &Opc) {
800 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
805 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
806 SDValue &Base, SDValue &Offset,
807 SDValue &Opc) {
853 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
854 SDValue &Offset, SDValue &Opc) {
873 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
874 SDValue &Base, SDValue &Offset) {
916 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
917 SDValue &Align) {
939 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
940 SDValue &Offset) {
953 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
954 SDValue &Offset, SDValue &Label) {
957 SDValue N1 = N.getOperand(1);
971 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
972 SDValue &Base, SDValue &Offset){
988 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
989 SDValue &Offset, unsigned Scale) {
991 SDValue TmpBase, TmpOffImm;
1023 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1024 SDValue &Base,
1025 SDValue &Offset) {
1030 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1031 SDValue &Base,
1032 SDValue &Offset) {
1037 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1038 SDValue &Base,
1039 SDValue &Offset) {
1044 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1045 SDValue &Base, SDValue &OffImm) {
1047 SDValue TmpBase, TmpOffImm;
1100 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1101 SDValue &OffImm) {
1106 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1107 SDValue &OffImm) {
1112 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1113 SDValue &OffImm) {
1117 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1118 SDValue &Base, SDValue &OffImm) {
1154 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1155 SDValue &Opc) {
1176 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1177 SDValue &Base, SDValue &OffImm) {
1229 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1230 SDValue &Base, SDValue &OffImm) {
1255 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1256 SDValue &OffImm){
1272 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1273 SDValue &Base,
1274 SDValue &OffReg, SDValue &ShImm) {
1325 static inline SDValue getAL(SelectionDAG *CurDAG) {
1336 SDValue Offset, AMOpc;
1383 SDValue Chain = LD->getChain();
1384 SDValue Base = LD->getBasePtr();
1385 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1390 SDValue Chain = LD->getChain();
1391 SDValue Base = LD->getBasePtr();
1392 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1410 SDValue Offset;
1439 SDValue Chain = LD->getChain();
1440 SDValue Base = LD->getBasePtr();
1441 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1452 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1454 SDValue RegClass =
1456 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1457 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1458 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1464 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1466 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1467 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1468 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1469 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1475 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1477 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1478 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1479 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1480 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1486 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1487 SDValue V2, SDValue V3) {
1489 SDValue RegClass =
1491 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1492 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1493 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1494 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1495 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1502 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1503 SDValue V2, SDValue V3) {
1505 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1506 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1507 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1508 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1509 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1510 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1517 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1518 SDValue V2, SDValue V3) {
1520 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1521 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1522 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1523 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1524 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1525 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1533 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1558 SDValue MemAddr, Align;
1563 SDValue Chain = N->getOperand(0);
1602 SDValue Pred = getAL(CurDAG);
1603 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1605 SmallVector<SDValue, 7> Ops;
1614 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1629 SDValue ImplDef =
1630 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1631 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1634 Chain = SDValue(VLdA, 2);
1637 Ops.push_back(SDValue(VLdA, 1));
1640 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1646 Ops.push_back(SDValue(VLdA, 0));
1663 SDValue SuperReg = SDValue(VLd, 0);
1668 ReplaceUses(SDValue(N, Vec),
1670 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1672 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1682 SDValue MemAddr, Align;
1691 SDValue Chain = N->getOperand(0);
1720 SDValue Pred = getAL(CurDAG);
1721 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1722 SmallVector<SDValue, 7> Ops;
1726 SDValue SrcReg;
1731 SDValue V0 = N->getOperand(Vec0Idx + 0);
1732 SDValue V1 = N->getOperand(Vec0Idx + 1);
1734 SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1736 SDValue V2 = N->getOperand(Vec0Idx + 2);
1739 SDValue V3 = (NumVecs == 3)
1740 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1742 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1746 SDValue Q0 = N->getOperand(Vec0Idx);
1747 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1748 SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1756 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1776 SDValue V0 = N->getOperand(Vec0Idx + 0);
1777 SDValue V1 = N->getOperand(Vec0Idx + 1);
1778 SDValue V2 = N->getOperand(Vec0Idx + 2);
1779 SDValue V3 = (NumVecs == 3)
1780 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1782 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1786 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1791 Chain = SDValue(VStA, 1);
1794 Ops.push_back(SDValue(VStA, 0));
1797 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1820 SDValue MemAddr, Align;
1829 SDValue Chain = N->getOperand(0);
1876 SDValue Pred = getAL(CurDAG);
1877 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1879 SmallVector<SDValue, 8> Ops;
1883 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1887 SDValue SuperReg;
1888 SDValue V0 = N->getOperand(Vec0Idx + 0);
1889 SDValue V1 = N->getOperand(Vec0Idx + 1);
1892 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1894 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1896 SDValue V2 = N->getOperand(Vec0Idx + 2);
1897 SDValue V3 = (NumVecs == 3)
1898 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1901 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1903 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1920 SuperReg = SDValue(VLdLn, 0);
1925 ReplaceUses(SDValue(N, Vec),
1927 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1929 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1938 SDValue MemAddr, Align;
1945 SDValue Chain = N->getOperand(0);
1972 SDValue Pred = getAL(CurDAG);
1973 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1974 SDValue SuperReg;
1976 SmallVector<SDValue, 6> Ops;
1980 SDValue Inc = N->getOperand(2);
1996 SuperReg = SDValue(VLdDup, 0);
2002 ReplaceUses(SDValue(N, Vec),
2004 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2006 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2018 SDValue RegSeq;
2019 SDValue V0 = N->getOperand(FirstTblReg + 0);
2020 SDValue V1 = N->getOperand(FirstTblReg + 1);
2022 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2024 SDValue V2 = N->getOperand(FirstTblReg + 2);
2027 SDValue V3 = (NumVecs == 3)
2028 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2030 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2033 SmallVector<SDValue, 6> Ops;
2069 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2070 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2092 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2093 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2104 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2105 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2106 SDValue CPTmp0;
2107 SDValue CPTmp1;
2121 SDValue SOShImm =
2123 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2124 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2131 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2132 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2133 SDValue CPTmp0;
2134 SDValue CPTmp1;
2135 SDValue CPTmp2;
2137 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2138 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2143 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2144 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2151 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2152 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2172 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2173 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2174 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2182 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2183 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2205 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2206 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2207 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2216 SDValue FalseVal = N->getOperand(0);
2217 SDValue TrueVal = N->getOperand(1);
2218 SDValue CC = N->getOperand(2);
2219 SDValue CCR = N->getOperand(3);
2220 SDValue InFlag = N->getOperand(4);
2230 SDValue CPTmp0;
2231 SDValue CPTmp1;
2232 SDValue CPTmp2;
2285 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2286 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2317 SDValue XORSrc0 = N->getOperand(0);
2318 SDValue XORSrc1 = N->getOperand(1);
2331 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2332 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2333 SDValue SRASrc0 = XORSrc1.getOperand(0);
2334 SDValue SRASrc1 = XORSrc1.getOperand(1);
2365 SmallVector<SDValue, 6> Ops;
2418 SDValue CPIdx =
2425 SDValue Pred = getAL(CurDAG);
2426 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2427 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2431 SDValue Ops[] = {
2441 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2451 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2453 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2459 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2483 SDValue V = N->getOperand(0);
2485 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2486 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2488 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2491 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2499 SDValue V = N->getOperand(0);
2501 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2502 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2504 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2507 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2531 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2536 SDValue N2 = N0.getOperand(1);
2545 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2547 SDValue Ops[] = { N0.getOperand(0), Imm16,
2562 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2567 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2579 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2583 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2617 SDValue Chain = N->getOperand(0);
2618 SDValue N1 = N->getOperand(1);
2619 SDValue N2 = N->getOperand(2);
2620 SDValue N3 = N->getOperand(3);
2621 SDValue InFlag = N->getOperand(4);
2626 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2629 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2632 Chain = SDValue(ResNode, 0);
2634 InFlag = SDValue(ResNode, 1);
2635 ReplaceUses(SDValue(N, 1), InFlag);
2637 ReplaceUses(SDValue(N, 0),
2638 SDValue(Chain.getNode(), Chain.getResNo()));
2657 SDValue Pred = getAL(CurDAG);
2658 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2659 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2676 SDValue Pred = getAL(CurDAG);
2677 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2678 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2695 SDValue Pred = getAL(CurDAG);
2696 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2697 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2888 SDValue MemAddr = N->getOperand(2);
2890 SDValue Chain = N->getOperand(0);
2903 SmallVector<SDValue, 7> Ops;
2919 SDValue(Ld, 0), SDValue(0,0));
2921 SDValue(Ld, 1), Chain.getValue(1));
2924 SDValue Glue = Chain.getValue(1);
2925 if (!SDValue(N, 0).use_empty()) {
2926 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2929 ReplaceUses(SDValue(N, 0), Result);
2931 if (!SDValue(N, 1).use_empty()) {
2932 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2935 ReplaceUses(SDValue(N, 1), Result);
2938 ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
2944 SDValue Chain = N->getOperand(0);
2945 SDValue Val0 = N->getOperand(2);
2946 SDValue Val1 = N->getOperand(3);
2947 SDValue MemAddr = N->getOperand(4);
2953 SDValue(0, 0));
2956 SDValue Glue = Chain.getValue(1);
2970 SmallVector<SDValue, 7> Ops;
3143 SmallVector<SDValue, 6> Ops;
3156 SDValue V0 = N->getOperand(0);
3157 SDValue V1 = N->getOperand(1);
3158 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3160 SmallVector<SDValue, 6> Ops;
3194 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3195 std::vector<SDValue> &OutOps) {
