Lines Matching refs:SDNode
979 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1855 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1862 SDNode* Copies[2];
1863 SDNode *Use = *N->use_begin();
1868 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1892 SDNode *Copy = Copies[i];
1893 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1896 SDNode *Use = *UI;
2826 SDNode *N = Op.getNode();
3212 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3348 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3360 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3395 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4495 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4500 SDNode *BVN = N->getOperand(0).getNode();
4527 SDNode *Elt = N->getOperand(i).getNode();
4548 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4558 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4568 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4578 SDNode *BVN = N->getOperand(0).getNode();
4601 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4604 SDNode *N0 = N->getOperand(0).getNode();
4605 SDNode *N1 = N->getOperand(1).getNode();
4612 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4615 SDNode *N0 = N->getOperand(0).getNode();
4616 SDNode *N1 = N->getOperand(1).getNode();
4628 SDNode *N0 = Op.getOperand(0).getNode();
4629 SDNode *N1 = Op.getOperand(1).getNode();
4905 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
4996 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6404 SDNode *Node) const {
6480 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
6541 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
6567 SDNode *V = Vec.getNode();
6632 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
6651 static SDValue PerformADDCombine(SDNode *N,
6668 static SDValue PerformSUBCombine(SDNode *N,
6690 static SDValue PerformVMULCombine(SDNode *N,
6718 static SDValue PerformMULCombine(SDNode *N,
6772 static SDValue PerformANDCombine(SDNode *N,
6808 static SDValue PerformORCombine(SDNode *N,
6990 static SDValue PerformBFICombine(SDNode *N,
7012 static SDValue PerformVMOVRRDCombine(SDNode *N,
7020 SDNode *InNode = InDouble.getNode();
7054 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
7072 static SDValue PerformSTORECombine(SDNode *N,
7127 static bool hasNormalLoadOperand(SDNode *N) {
7130 SDNode *Elt = N->getOperand(i).getNode();
7139 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
7173 static SDValue PerformInsertEltCombine(SDNode *N,
7178 SDNode *Elt = N->getOperand(1).getNode();
7199 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
7252 static SDValue CombineBaseUpdate(SDNode *N,
7264 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7266 SDNode *User = *UI;
7386 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
7394 SDNode *VLD = N->getOperand(0).getNode();
7417 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7422 SDNode *User = *UI;
7442 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7448 SDNode *User = *UI;
7465 static SDValue PerformVDUPLANECombine(SDNode *N,
7530 static SDValue PerformVCVTCombine(SDNode *N,
7566 static SDValue PerformVDIVCombine(SDNode *N,
7642 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
7807 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
7842 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
7882 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
7967 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
8030 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
8320 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
8379 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
8408 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8446 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
