Lines Matching refs:MemOps
95 MemOpQueue &MemOps,
111 unsigned Scratch, MemOpQueue &MemOps,
114 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
365 // MergeOpsUpdate - call MergeOps and update MemOps and merges accordingly on
368 MemOpQueue &memOps,
379 const unsigned insertPos = memOps[insertAfter].Position;
382 for (unsigned i = 0, e = memOps.size(); i != e; ++i) {
388 if (memOps[i].Position < insertPos && memOps[i].isKill) {
389 unsigned Reg = memOps[i].Reg;
397 unsigned Reg = memOps[i].Reg;
400 bool isKill = memOps[i].isKill || KilledRegs.count(Reg);
405 MachineBasicBlock::iterator Loc = memOps[insertAfter].MBBI;
414 // Remove kill flags from any memops that come before insertPos.
419 int Idx = memOps[j].MBBI->findRegisterUseOperandIdx(Reg, true);
421 memOps[j].MBBI->getOperand(Idx).setIsKill(false);
422 memOps[j].isKill = false;
424 memOps[i].isKill = true;
426 MBB.erase(memOps[i].MBBI);
429 memOps[i].Merged = true;
430 memOps[i].MBBI = Merges.back();
431 memOps[i].Position = insertPos;
441 unsigned Scratch, MemOpQueue &MemOps,
444 int Offset = MemOps[SIndex].Offset;
447 MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI;
474 MemOps.size(); i != e; ++i) {
475 int NewOffset = MemOps[i].Offset;
476 const MachineOperand &MO = MemOps[i].MBBI->getOperand(0);
492 MergeOpsUpdate(MBB, MemOps, SIndex, i, insertAfter, SOffset,
495 MemOps, Merges);
499 if (MemOps[i].Position > MemOps[insertAfter].Position)
504 MergeOpsUpdate(MBB, MemOps, SIndex, MemOps.size(), insertAfter, SOffset,
1006 void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) {
1007 MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
1008 unsigned Position = MemOps[0].Position;
1009 for (unsigned i = 1, e = MemOps.size(); i != e; ++i) {
1010 if (MemOps[i].Position < Position) {
1011 Position = MemOps[i].Position;
1012 Loc = MemOps[i].MBBI;
1181 MemOpQueue MemOps;
1228 MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill, Position, MBBI));
1240 if (Offset > MemOps.back().Offset) {
1241 MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill,
1246 for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end();
1249 MemOps.insert(I, MemOpQueueEntry(Offset, Reg, isKill,
1282 AdvanceRS(MBB, MemOps);
1291 CurrPred, CurrPredReg, Scratch, MemOps, Merges);
1303 if (!MemOps[i].Merged)
1304 if (MergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
1312 if (MergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) {
1324 MemOps.clear();
1457 SmallPtrSet<MachineInstr*, 4> &MemOps,
1465 if (I->isDebugValue() || MemOps.count(&*I))
1638 SmallPtrSet<MachineInstr*, 4> MemOps;
1641 MemOps.insert(Ops[i]);
1650 MemOps, MemRegs, TRI);
1658 && (MemOps.count(InsertPos) || InsertPos->isDebugValue()))
