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Lines Matching refs:getKillRegState

345       .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
356     .addReg(Base, getKillRegState(BaseKill))
360                      | getKillRegState(Regs[i].second));
749     .addReg(Base, getKillRegState(BaseKill))
904       .addReg(Base, getKillRegState(isLd ? BaseKill : false))
907                             getKillRegState(MO.isKill())));
938         .addReg(MO.getReg(), getKillRegState(MO.isKill()))
944         .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1057       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1062       .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1063       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1108           .addReg(BaseReg, getKillRegState(BaseKill))
1115           .addReg(BaseReg, getKillRegState(BaseKill))
1118                   getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
1120                   getKillRegState(OddDeadKill)  | getUndefRegState(OddUndef));