Lines Matching refs:ARM_AM
90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
341 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
351 ARM_AM::ShiftOpc ShiftTy;
360 ARM_AM::ShiftOpc ShiftTy;
366 ARM_AM::ShiftOpc ShiftTy;
654 return ARM_AM::getSOImmVal(Value) != -1;
662 return ARM_AM::getT2SOImmVal(Value) != -1;
686 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
719 if (Memory.ShiftType != ARM_AM::no_shift) return false;
731 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
751 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
757 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
772 if (Memory.ShiftType == ARM_AM::no_shift)
774 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
782 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1056 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1064 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1249 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1253 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1257 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1270 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1274 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1283 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1287 Val = ARM_AM::getAM3Opc(AddSub, Val);
1291 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1302 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1311 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1315 Val = ARM_AM::getAM3Opc(AddSub, Val);
1324 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1328 Val = ARM_AM::getAM5Opc(AddSub, Val);
1407 unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1489 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1490 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1652 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1667 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1767 ARM_AM::ShiftOpc ShiftType,
1786 ARM_AM::ShiftOpc ShiftTy,
1829 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1872 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1873 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1896 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1898 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1904 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1905 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
2029 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2030 .Case("lsl", ARM_AM::lsl)
2031 .Case("lsr", ARM_AM::lsr)
2032 .Case("asr", ARM_AM::asr)
2033 .Case("ror", ARM_AM::ror)
2034 .Case("rrx", ARM_AM::rrx)
2035 .Default(ARM_AM::no_shift);
2037 if (ShiftTy == ARM_AM::no_shift)
2051 if (ShiftTy == ARM_AM::rrx) {
2077 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2078 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2096 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2923 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3001 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3329 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3379 ARM_AM::no_shift, 0, Align,
3424 ARM_AM::no_shift, 0, 0,
3453 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3485 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3493 St = ARM_AM::lsl;
3495 St = ARM_AM::lsr;
3497 St = ARM_AM::asr;
3499 St = ARM_AM::ror;
3501 St = ARM_AM::rrx;
3508 if (St != ARM_AM::rrx) {
3527 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3528 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3573 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
