Lines Matching refs:VECTOR_SHUFFLE
699 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
800 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
850 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
861 setOperationAction(ISD::VECTOR_SHUFFLE,
869 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
870 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1069 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1138 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
3227 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3309 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3373 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3428 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3448 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3466 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3485 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3505 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3554 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3602 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3645 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3669 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3697 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3755 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3787 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3905 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3933 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3961 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3983 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4060 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4076 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4092 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4152 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4265 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4366 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4378 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4390 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4494 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4523 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4737 // vector_shuffle V1, V2 <1, 2, 3, X>
4770 // vector_shuffle V1, V2 <X, X, 4, 5>
5625 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE &&
5654 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE &&
5841 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6034 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6502 // a vector_shuffle operation without using a target specific node, because
6579 // The general ideia is that no vector_shuffle operation should be left to
6717 // new vector_shuffle with the corrected mask.
10394 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10849 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10850 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12393 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12409 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12468 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12477 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12502 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12509 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13102 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13824 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
13825 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
13830 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
13831 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
13838 // LHS = VECTOR_SHUFFLE A, B, LMask
13840 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
13845 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
13859 // RHS = VECTOR_SHUFFLE C, D, RMask
13862 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
13895 // LHS = VECTOR_SHUFFLE A, B, LMask
13896 // RHS = VECTOR_SHUFFLE A, B, RMask
14225 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
