Lines Matching refs:x04
38 0x04 (E)xclusive cache state
45 0x04 Exclusive-state line from L2
52 0x04 Store pipe ops excluding load ops and SSE move ops
60 0x04 SS register
68 0x04 SSE instructions (SSE, SSE2, SSE3, and SSE4A)
72 0x04 With low op in position 2
76 0x04 SSE reclass microfaults
81 0x04 DCT0 Page conflict
91 0x04 DCT0 Write to read turnaround
98 0x04 DCT0 DCQ bypass
106 0x04 Posted write byte (1-32 bytes)
113 0x04 Probe hit dirty without memory cancel
122 0x04 TLB fill (page table walks)
129 0x04 TLB page table walk
137 0x04 GART miss
176 0x04 Read Block (Dcache load miss refill)
190 0x04 Shared
196 0x04 L2 1G TLB hit (RevC)
200 0x04 1G TLB reload
204 0x04 Load pipe error
209 0x04 NTA (PrefetchNTA)
215 0x04 Number of times the HTC trip point is crossed
223 0x04 Prefetch Request
232 0x04 Buffer release DWORD sent
240 0x04 Cycles in non-speculative phase (including cache miss penalty)
245 0x04 Single precision divide/square root ops
253 0x04 All other merging move uops
258 0x04 x87 bottom-executing uops retired
266 0x04 Misaligned
270 0x04 (E)xclusive cache state
278 0x04 L1 1G TLB hit
288 0x04 From local node to node 2
297 0x04 From local node to node 2
306 0x04 Read block modified
315 0x04 Read block modified
324 0x04 Victim block
333 0x04 Read block Modify
341 0x04 Owned
350 0x04 Owned
358 0x04 Host page size is larger than the guest page size
362 0x04 Divide ops
370 0x04 RbBlkM
