Lines Matching refs:uint32_t
64 int srcreg, int operand, uint32_t value,
66 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
84 uint32_t regs[16];
88 uint32_t uncached_cpsr;
89 uint32_t spsr;
92 uint32_t banked_spsr[7];
93 uint32_t banked_r13[7];
94 uint32_t banked_r14[7];
97 uint32_t usr_regs[5];
98 uint32_t fiq_regs[5];
101 uint32_t CF; /* 0 or 1 */
102 uint32_t VF; /* V is the bit 31. All other bits are undefined */
103 uint32_t NF; /* N is bit 31. All other bits are undefined. */
104 uint32_t ZF; /* Z set if zero. */
105 uint32_t QF; /* 0 or 1 */
106 uint32_t GE; /* cpsr[19:16] */
107 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
108 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
112 uint32_t c0_cpuid;
113 uint32_t c0_cachetype;
114 uint32_t c0_ccsid[16]; /* Cache size. */
115 uint32_t c0_clid; /* Cache level. */
116 uint32_t c0_cssel; /* Cache size selection. */
117 uint32_t c0_c1[8]; /* Feature registers. */
118 uint32_t c0_c2[8]; /* Instruction set registers. */
119 uint32_t c1_sys; /* System control register. */
120 uint32_t c1_coproc; /* Coprocessor access register. */
121 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
122 uint32_t c1_secfg; /* Secure configuration register. */
123 uint32_t c1_sedbg; /* Secure debug enable register. */
124 uint32_t c1_nseac; /* Non-secure access control register. */
125 uint32_t c2_base0; /* MMU translation table base 0. */
126 uint32_t c2_base1; /* MMU translation table base 1. */
127 uint32_t c2_control; /* MMU translation table base control. */
128 uint32_t c2_mask; /* MMU translation table base selection mask. */
129 uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
130 uint32_t c2_data; /* MPU data cachable bits. */
131 uint32_t c2_insn; /* MPU instruction cachable bits. */
132 uint32_t c3; /* MMU domain access control register
134 uint32_t c5_insn; /* Fault status registers. */
135 uint32_t c5_data;
136 uint32_t c6_region[8]; /* MPU base/size registers. */
137 uint32_t c6_insn; /* Fault address registers. */
138 uint32_t c6_data;
139 uint32_t c7_par; /* Translation result. */
140 uint32_t c9_insn; /* Cache lockdown registers. */
141 uint32_t c9_data;
142 uint32_t c9_pmcr_data; /* Performance Monitor Control Register */
143 uint32_t c9_useren; /* user enable register */
144 uint32_t c9_inten; /* interrupt enable set/clear register */
145 uint32_t c12_vbar; /* secure/nonsecure vector base address register. */
146 uint32_t c12_mvbar; /* monitor vector base address register. */
147 uint32_t c13_fcse; /* FCSE PID. */
148 uint32_t c13_context; /* Context ID. */
149 uint32_t c13_tls1; /* User RW Thread register. */
150 uint32_t c13_tls2; /* User RO Thread register. */
151 uint32_t c13_tls3; /* Privileged Thread register. */
152 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
153 uint32_t c15_ticonfig; /* TI925T configuration byte. */
154 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
155 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
156 uint32_t c15_threadid; /* TI debugger thread-ID. */
160 uint32_t other_sp;
161 uint32_t vecbase;
162 uint32_t basepri;
163 uint32_t control;
170 uint32_t cp14_dbgdidr;
173 uint32_t teecr;
174 uint32_t teehbr;
177 uint32_t features;
183 uint32_t xregs[16];
189 uint32_t scratch[8];
206 uint32_t exclusive_addr;
207 uint32_t exclusive_val;
208 uint32_t exclusive_high;
210 uint32_t exclusive_test;
211 uint32_t exclusive_info;
219 uint32_t cregs[16];
247 uint32_t do_arm_semihosting(CPUARMState *env);
289 uint32_t cpsr_read(CPUARMState *env);
291 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
294 static inline uint32_t xpsr_read(CPUARMState *env)
306 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
332 uint32_t vfp_get_fpscr(CPUARMState *env);
333 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
