Lines Matching refs:tcg_out32
289 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
296 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
303 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
314 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
361 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
371 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
374 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
382 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
386 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
395 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
419 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
424 tcg_out32(s, RDY | INSN_RD(rd));
478 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
482 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
494 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
499 tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
624 tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
651 tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
696 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
698 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
784 tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
795 tcg_out32(s, 0);
805 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
855 tcg_out32(s, 0);
996 tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
1007 tcg_out32(s, 0);
1020 tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
1036 tcg_out32(s, 0);
1124 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
1126 tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1133 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1139 tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1147 tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1153 tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
