Lines Matching refs:TCGV_LOW
774 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
781 tcg_gen_movi_i32(TCGV_LOW(ret), arg);
788 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
795 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
802 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
809 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
810 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
816 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
823 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
824 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
834 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
836 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
844 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
850 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
856 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
864 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
866 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
873 tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
874 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
880 tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
881 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
887 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
893 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
899 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
905 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
911 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
917 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
975 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
982 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
983 TCGV_LOW(arg1), TCGV_HIGH(arg1),
984 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
996 tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
997 TCGV_LOW(arg1), TCGV_LOW(arg2));
999 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
1001 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
1497 tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1498 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1503 tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1504 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1509 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1510 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1515 tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1521 tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1527 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1533 tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1538 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1544 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1545 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1552 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1559 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1568 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1570 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1778 tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1793 tcg_gen_discard_i32(TCGV_LOW(arg));
1806 tcg_gen_mov_i32(TCGV_LOW(dest), low);
1823 tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1851 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1877 tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1900 tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1923 tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1949 tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
2195 tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2206 tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2208 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2217 tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2228 tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2230 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2239 tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2250 tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2252 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2259 tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2261 tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2262 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2271 tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2281 tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2291 tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2299 tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2302 tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2303 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
