Lines Matching refs:VG_
47 VG_(dmsg)("warning: Pentium 4 with %d KB micro-op instruction trace cache\n",
49 VG_(dmsg)(" Simulating a %d KB I-cache with %d B lines\n",
81 VG_(dmsg)("warning: CPUID level < 2 for Intel processor (%d)\n", level);
86 VG_(cpuid)(1, &cpuid1_eax, &cpuid1_ignore,
91 VG_(cpuid)(2, (Int*)&info[0], (Int*)&info[4],
97 VG_(dmsg)("warning: non-zero CPUID trials for Intel processor (%d)\n",
133 VG_(tool_panic)("IA-64 cache detected?!");
241 VG_(dmsg)("warning: Unknown Intel cache config value (0x%x), ignoring\n",
249 VG_(dmsg)("warning: L3 cache found, using its data for the LL simulation.\n");
255 VG_(dmsg)("warning: L2 cache not installed, ignore LL results.\n");
314 VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy);
317 VG_(dmsg)("warning: ext_level < 0x80000006 for AMD processor (0x%x)\n",
322 VG_(cpuid)(0x80000005, &dummy, &dummy, &D1i, &I1i);
323 VG_(cpuid)(0x80000006, &dummy, &dummy, &L2i, &L3i);
325 VG_(cpuid)(0x1, &model, &dummy, &dummy, &dummy);
329 VG_(dmsg)("warning: Buggy Duron stepping A0. Assuming L2 size=65536 bytes\n");
353 VG_(dmsg)("warning: L3 cache found, using its data for the L2 simulation.\n");
365 if (!VG_(has_cpuid)()) {
366 VG_(dmsg)("CPUID instruction not supported\n");
370 VG_(cpuid)(0, &level, (int*)&vendor_id[0],
375 VG_(dmsg)("CPUID level is 0, early Pentium?\n");
380 if (0 == VG_(strcmp)(vendor_id, "GenuineIntel")) {
383 } else if (0 == VG_(strcmp)(vendor_id, "AuthenticAMD")) {
386 } else if (0 == VG_(strcmp)(vendor_id, "CentaurHauls")) {
400 VG_(dmsg)("CPU vendor ID not recognised (%s)\n", vendor_id);
413 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc,
428 VG_(dmsg)("Warning: Couldn't auto-detect cache config, using one "
