Lines Matching refs:MODE
38 /* Define __arm__ even when in thumb mode, for \
249 /* We could use unified syntax for arm mode, but for now we just use it
280 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
471 in a wider mode than that declared by the program. In such cases,
473 type, but kept valid in the wider mode. The signedness of the
478 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
479 if (GET_MODE_CLASS (MODE) == MODE_INT \
480 && GET_MODE_SIZE (MODE) < 4) \
482 if (MODE == QImode) \
484 else if (MODE == HImode) \
486 (MODE) = SImode; \
489 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
490 if ((GET_MODE_CLASS (MODE) == MODE_INT \
491 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
492 && GET_MODE_SIZE (MODE) < 4) \
493 (MODE) = SImode; \
500 Most ARM processors are run in little endian mode, so that is the default.
507 This is always false, even when in big-endian mode. */
528 #define UNITS_PER_SIMD_WORD(MODE) \
545 /* The lowest bit is used to indicate Thumb-mode functions, so the
874 /* The number of (integer) registers required to hold a quantity of type MODE.
876 #define ARM_NUM_REGS(MODE) \
877 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
879 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
880 #define ARM_NUM_REGS2(MODE, TYPE) \
881 ARM_NUM_INTS ((MODE) == BLKmode ? \
882 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
1039 to hold something of mode MODE.
1040 This is ordinarily the length in words of a value of mode MODE
1044 mode. */
1045 #define HARD_REGNO_NREGS(REGNO, MODE) \
1051 ? 1 : ARM_NUM_REGS (MODE))
1053 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1054 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1055 arm_hard_regno_mode_ok ((REGNO), (MODE))
1058 when one has mode MODE1 and one has mode MODE2.
1064 #define VALID_IWMMXT_REG_MODE(MODE) \
1065 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1068 #define VALID_NEON_DREG_MODE(MODE) \
1069 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1070 || (MODE) == V2SFmode || (MODE) == DImode)
1073 #define VALID_NEON_QREG_MODE(MODE) \
1074 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1075 || (MODE) == V4SFmode || (MODE) == V2DImode)
1078 #define VALID_NEON_STRUCT_MODE(MODE) \
1079 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1080 || (MODE) == CImode || (MODE) == XImode)
1233 precision. VFP registers may only be accessed in the mode they
1253 when addressing quantities in QI or HI mode; if we don't know the
1254 mode, then we must be conservative. */
1255 #define MODE_BASE_REG_CLASS(MODE) \
1257 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1261 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1280 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1283 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1287 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1290 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1295 or out of a register in CLASS in MODE. If it can be done directly,
1297 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1301 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1303 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1305 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1307 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1310 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1314 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1316 coproc_secondary_reload_class (MODE, X, TRUE) : \
1326 (((MODE) == HImode && ! arm_arch4 \
1331 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1340 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1346 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1352 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
1357 else if (MODE == SImode \
1358 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1359 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1362 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1365 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1386 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1402 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1404 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1412 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1414 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1416 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1419 needed to represent mode MODE in a register of class CLASS.
1420 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
1421 #define CLASS_MAX_NREGS(CLASS, MODE) \
1422 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
1425 operand of a SUBREG that changes the mode of the object illegally. */
1428 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1502 assuming the value has mode MODE. */
1503 #define LIBCALL_VALUE(MODE) \
1505 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1506 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
1508 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1509 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
1510 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
1511 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
1512 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1581 Only soft_frame is used in thumb mode. */
1647 MODE is the argument's machine mode.
1661 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1662 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1664 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1665 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1667 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1668 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1683 of mode MODE and data type TYPE.
1685 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1687 if (arm_vector_mode_supported_p (MODE) \
1692 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
1695 argument with the specified mode and type. If it is not defined,
1697 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
1698 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1855 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1894 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1958 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1960 || (GET_MODE_SIZE (MODE) >= 4 \
1963 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1965 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1968 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1970 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1973 /* For ARM code, we don't care about the mode, but for Thumb, the index
2127 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2130 || (GET_MODE_SIZE (MODE) >= 4 \
2145 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2146 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
2154 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2156 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2172 /* Nonzero if X can be the base register in a reg+reg addressing mode.
2174 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2180 The MODE argument is the machine mode for the MEM expression
2189 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2191 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
2195 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2197 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2201 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2203 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2207 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2209 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2211 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2213 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2219 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2221 X = arm_legitimize_address (X, OLDX, MODE); \
2225 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2229 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2231 X = thumb_legitimize_address (X, OLDX, MODE); \
2234 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2237 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2239 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2241 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2243 if (memory_address_p (MODE, X)) \
2248 has an effect that depends on the machine mode it is used for. */
2264 /* Specify the machine mode that this machine uses
2289 on the full register even if a narrower mode is specified. */
2292 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2296 #define LOAD_EXTEND_OP(MODE) \
2298 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2299 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2304 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2382 return the mode to be used for the comparison. */
2386 #define REVERSIBLE_CC_MODE(MODE) 1
2388 #define REVERSE_CONDITION(CODE,MODE) \
2389 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2409 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
2689 when running in 26-bit mode. */
2702 in 26 bit mode, the condition codes must be masked out of the \
2704 when running in 32 bit mode. */ \
