1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides ARM specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef ARMMCTARGETDESC_H 15 #define ARMMCTARGETDESC_H 16 17 #include "llvm/Support/DataTypes.h" 18 #include <string> 19 20 namespace llvm { 21 class MCAsmBackend; 22 class MCCodeEmitter; 23 class MCContext; 24 class MCInstrInfo; 25 class MCObjectWriter; 26 class MCSubtargetInfo; 27 class StringRef; 28 class Target; 29 class raw_ostream; 30 31 extern Target TheARMTarget, TheThumbTarget; 32 33 namespace ARM_MC { 34 std::string ParseARMTriple(StringRef TT); 35 36 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. 37 /// This is exposed so Asm parser, etc. do not need to go through 38 /// TargetRegistry. 39 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, 40 StringRef FS); 41 } 42 43 MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII, 44 const MCSubtargetInfo &STI, 45 MCContext &Ctx); 46 47 MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT); 48 49 /// createARMMachObjectWriter - Construct an ARM Mach-O object writer. 50 MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS, 51 bool Is64Bit, 52 uint32_t CPUType, 53 uint32_t CPUSubtype); 54 55 } // End llvm namespace 56 57 // Defines symbolic names for ARM registers. This defines a mapping from 58 // register name to register number. 59 // 60 #define GET_REGINFO_ENUM 61 #include "ARMGenRegisterInfo.inc" 62 63 // Defines symbolic names for the ARM instructions. 64 // 65 #define GET_INSTRINFO_ENUM 66 #include "ARMGenInstrInfo.inc" 67 68 #define GET_SUBTARGETINFO_ENUM 69 #include "ARMGenSubtargetInfo.inc" 70 71 #endif 72
