| /external/libffi/linux-sh/ |
| ffi.h | 6 #define SH
7 #include "../src/sh/ffitarget.h"
|
| /external/skia/gm/ |
| strokerects.cpp | 28 static const SkScalar SH = SkIntToScalar(H);
65 canvas->translate(SW * x, SH * y);
68 , SW - SkIntToScalar(2), SH - SkIntToScalar(2)
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 38 unsigned char SH = MI->getOperand(2).getImm();
42 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
45 if (SH <= 31 && MB == (32-SH) && ME == 31) {
47 SH = 32-SH;
53 O << ", " << (unsigned int)SH;
71 unsigned char SH = MI->getOperand(2).getImm();
73 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, S
[all...] |
| /external/strace/android/arch/sh/ |
| config.h | 368 /* Define for the SH architecture. */
369 #define SH 1
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 88 unsigned &SH, unsigned &MB, unsigned &ME);
332 bool isShiftMask, unsigned &SH,
366 SH = Shift & 31;
390 unsigned Value, SH = 0;
422 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
429 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
435 SH &= 31;
436 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 400 #define SH(s) ((s)<<11)
559 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
574 | SH (0)
755 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
770 | SH (0)
807 | SH (0)
815 | SH (0)
1125 int crop, sh, arg; local
1152 | SH (27)
1192 sh = 30
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 397 #define SH(s) ((s)<<11)
443 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
445 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
578 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
588 | SH (0)
1053 int crop, sh, arg local
1479 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1); local
[all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 235 SH = ((5 << 3) + 1) << kOpcodeShift,
|
| /external/qemu/ |
| ppc-dis.c | 753 /* The SH field in an X or M form instruction. */
754 #define SH RSO + 1
757 #define EVUIMM SH
760 /* The SH field in an MD form instruction. This is split. */
761 #define SH6 SH + 1
765 /* The SH field of the tlbwe instruction, which is optional. */
883 /* SH field starting at bit position 16. */
[all...] |
