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    Searched defs:SetCC (Results 1 - 6 of 6) sorted by null

  /external/v8/src/ia32/
disasm-ia32.cc 342 int SetCC(byte* data);
639 int DisassemblerIA32::SetCC(byte* data) {
991 data += SetCC(data);
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  /external/v8/src/x64/
disasm-x64.cc 427 int SetCC(byte* data);
821 int DisassemblerX64::SetCC(byte* data) {
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  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 69 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
518 // Get the SETCC result using the canonical SETCC type.
519 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
524 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
774 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break
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DAGCombiner.cpp 495 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
496 // that selects between the values 1 and 0, making it equivalent to a setcc.
502 if (N.getOpcode() == ISD::SETCC) {
521 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
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  /external/v8/src/arm/
constants-arm.h 274 SetCC = 1 << 20, // Set condition code.
  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp 182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
424 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
428 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
432 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
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