1 /************************************************************************** 2 Etherboot - BOOTP/TFTP Bootstrap Program 3 Intel EEPRO/10 NIC driver for Etherboot 4 Adapted from Linux eepro.c from kernel 2.2.17 5 6 This board accepts a 32 pin EEPROM (29C256), however a test with a 7 27C010 shows that this EPROM also works in the socket, but it's not clear 8 how repeatably. The two top address pins appear to be held low, thus 9 the bottom 32kB of the 27C010 is visible in the CPU's address space. 10 To be sure you could put 4 copies of the code in the 27C010, then 11 it doesn't matter whether the extra lines are held low or high, just 12 hopefully not floating as CMOS chips don't like floating inputs. 13 14 Be careful with seating the EPROM as the socket on my board actually 15 has 34 pins, the top row of 2 are not used. 16 ***************************************************************************/ 17 18 /* 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License as 21 * published by the Free Software Foundation; either version 2, or (at 22 * your option) any later version. 23 */ 24 25 /* to get some global routines like printf */ 26 #include "etherboot.h" 27 /* to get the interface to the body of the program */ 28 #include "nic.h" 29 /* to get our own prototype */ 30 #include "cards.h" 31 /* we use timer2 for microsecond waits */ 32 #include "timer.h" 33 34 #undef DEBUG /* only after include files */ 35 36 /* Different 82595 chips */ 37 #define LAN595 0 38 #define LAN595TX 1 39 #define LAN595FX 2 40 #define LAN595FX_10ISA 3 41 42 #define SLOW_DOWN inb(0x80); 43 44 /* The station (ethernet) address prefix, used for IDing the board. */ 45 #define SA_ADDR0 0x00 /* Etherexpress Pro/10 */ 46 #define SA_ADDR1 0xaa 47 #define SA_ADDR2 0x00 48 49 #define GetBit(x,y) ((x & (1<<y))>>y) 50 51 /* EEPROM Word 0: */ 52 #define ee_PnP 0 /* Plug 'n Play enable bit */ 53 #define ee_Word1 1 /* Word 1? */ 54 #define ee_BusWidth 2 /* 8/16 bit */ 55 #define ee_FlashAddr 3 /* Flash Address */ 56 #define ee_FlashMask 0x7 /* Mask */ 57 #define ee_AutoIO 6 /* */ 58 #define ee_reserved0 7 /* =0! */ 59 #define ee_Flash 8 /* Flash there? */ 60 #define ee_AutoNeg 9 /* Auto Negotiation enabled? */ 61 #define ee_IO0 10 /* IO Address LSB */ 62 #define ee_IO0Mask 0x /*...*/ 63 #define ee_IO1 15 /* IO MSB */ 64 65 /* EEPROM Word 1: */ 66 #define ee_IntSel 0 /* Interrupt */ 67 #define ee_IntMask 0x7 68 #define ee_LI 3 /* Link Integrity 0= enabled */ 69 #define ee_PC 4 /* Polarity Correction 0= enabled */ 70 #define ee_TPE_AUI 5 /* PortSelection 1=TPE */ 71 #define ee_Jabber 6 /* Jabber prevention 0= enabled */ 72 #define ee_AutoPort 7 /* Auto Port Selection 1= Disabled */ 73 #define ee_SMOUT 8 /* SMout Pin Control 0= Input */ 74 #define ee_PROM 9 /* Flash EPROM / PROM 0=Flash */ 75 #define ee_reserved1 10 /* .. 12 =0! */ 76 #define ee_AltReady 13 /* Alternate Ready, 0=normal */ 77 #define ee_reserved2 14 /* =0! */ 78 #define ee_Duplex 15 79 80 /* Word2,3,4: */ 81 #define ee_IA5 0 /*bit start for individual Addr Byte 5 */ 82 #define ee_IA4 8 /*bit start for individual Addr Byte 5 */ 83 #define ee_IA3 0 /*bit start for individual Addr Byte 5 */ 84 #define ee_IA2 8 /*bit start for individual Addr Byte 5 */ 85 #define ee_IA1 0 /*bit start for individual Addr Byte 5 */ 86 #define ee_IA0 8 /*bit start for individual Addr Byte 5 */ 87 88 /* Word 5: */ 89 #define ee_BNC_TPE 0 /* 0=TPE */ 90 #define ee_BootType 1 /* 00=None, 01=IPX, 10=ODI, 11=NDIS */ 91 #define ee_BootTypeMask 0x3 92 #define ee_NumConn 3 /* Number of Connections 0= One or Two */ 93 #define ee_FlashSock 4 /* Presence of Flash Socket 0= Present */ 94 #define ee_PortTPE 5 95 #define ee_PortBNC 6 96 #define ee_PortAUI 7 97 #define ee_PowerMgt 10 /* 0= disabled */ 98 #define ee_CP 13 /* Concurrent Processing */ 99 #define ee_CPMask 0x7 100 101 /* Word 6: */ 102 #define ee_Stepping 0 /* Stepping info */ 103 #define ee_StepMask 0x0F 104 #define ee_BoardID 4 /* Manucaturer Board ID, reserved */ 105 #define ee_BoardMask 0x0FFF 106 107 /* Word 7: */ 108 #define ee_INT_TO_IRQ 0 /* int to IRQ Mapping = 0x1EB8 for Pro/10+ */ 109 #define ee_FX_INT2IRQ 0x1EB8 /* the _only_ mapping allowed for FX chips */ 110 111 /*..*/ 112 #define ee_SIZE 0x40 /* total EEprom Size */ 113 #define ee_Checksum 0xBABA /* initial and final value for adding checksum */ 114 115 116 /* Card identification via EEprom: */ 117 #define ee_addr_vendor 0x10 /* Word offset for EISA Vendor ID */ 118 #define ee_addr_id 0x11 /* Word offset for Card ID */ 119 #define ee_addr_SN 0x12 /* Serial Number */ 120 #define ee_addr_CRC_8 0x14 /* CRC over last thee Bytes */ 121 122 123 #define ee_vendor_intel0 0x25 /* Vendor ID Intel */ 124 #define ee_vendor_intel1 0xD4 125 #define ee_id_eepro10p0 0x10 /* ID for eepro/10+ */ 126 #define ee_id_eepro10p1 0x31 127 128 /* now this section could be used by both boards: the oldies and the ee10: 129 * ee10 uses tx buffer before of rx buffer and the oldies the inverse. 130 * (aris) 131 */ 132 #define RAM_SIZE 0x8000 133 134 #define RCV_HEADER 8 135 #define RCV_DEFAULT_RAM 0x6000 136 #define RCV_RAM rcv_ram 137 138 static unsigned rcv_ram = RCV_DEFAULT_RAM; 139 140 #define XMT_HEADER 8 141 #define XMT_RAM (RAM_SIZE - RCV_RAM) 142 143 #define XMT_START ((rcv_start + RCV_RAM) % RAM_SIZE) 144 145 #define RCV_LOWER_LIMIT (rcv_start >> 8) 146 #define RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8) 147 #define XMT_LOWER_LIMIT (XMT_START >> 8) 148 #define XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8) 149 150 #define RCV_START_PRO 0x00 151 #define RCV_START_10 XMT_RAM 152 /* by default the old driver */ 153 static unsigned rcv_start = RCV_START_PRO; 154 155 #define RCV_DONE 0x0008 156 #define RX_OK 0x2000 157 #define RX_ERROR 0x0d81 158 159 #define TX_DONE_BIT 0x0080 160 #define CHAIN_BIT 0x8000 161 #define XMT_STATUS 0x02 162 #define XMT_CHAIN 0x04 163 #define XMT_COUNT 0x06 164 165 #define BANK0_SELECT 0x00 166 #define BANK1_SELECT 0x40 167 #define BANK2_SELECT 0x80 168 169 /* Bank 0 registers */ 170 #define COMMAND_REG 0x00 /* Register 0 */ 171 #define MC_SETUP 0x03 172 #define XMT_CMD 0x04 173 #define DIAGNOSE_CMD 0x07 174 #define RCV_ENABLE_CMD 0x08 175 #define RCV_DISABLE_CMD 0x0a 176 #define STOP_RCV_CMD 0x0b 177 #define RESET_CMD 0x0e 178 #define POWER_DOWN_CMD 0x18 179 #define RESUME_XMT_CMD 0x1c 180 #define SEL_RESET_CMD 0x1e 181 #define STATUS_REG 0x01 /* Register 1 */ 182 #define RX_INT 0x02 183 #define TX_INT 0x04 184 #define EXEC_STATUS 0x30 185 #define ID_REG 0x02 /* Register 2 */ 186 #define R_ROBIN_BITS 0xc0 /* round robin counter */ 187 #define ID_REG_MASK 0x2c 188 #define ID_REG_SIG 0x24 189 #define AUTO_ENABLE 0x10 190 #define INT_MASK_REG 0x03 /* Register 3 */ 191 #define RX_STOP_MASK 0x01 192 #define RX_MASK 0x02 193 #define TX_MASK 0x04 194 #define EXEC_MASK 0x08 195 #define ALL_MASK 0x0f 196 #define IO_32_BIT 0x10 197 #define RCV_BAR 0x04 /* The following are word (16-bit) registers */ 198 #define RCV_STOP 0x06 199 200 #define XMT_BAR_PRO 0x0a 201 #define XMT_BAR_10 0x0b 202 static unsigned xmt_bar = XMT_BAR_PRO; 203 204 #define HOST_ADDRESS_REG 0x0c 205 #define IO_PORT 0x0e 206 #define IO_PORT_32_BIT 0x0c 207 208 /* Bank 1 registers */ 209 #define REG1 0x01 210 #define WORD_WIDTH 0x02 211 #define INT_ENABLE 0x80 212 #define INT_NO_REG 0x02 213 #define RCV_LOWER_LIMIT_REG 0x08 214 #define RCV_UPPER_LIMIT_REG 0x09 215 216 #define XMT_LOWER_LIMIT_REG_PRO 0x0a 217 #define XMT_UPPER_LIMIT_REG_PRO 0x0b 218 #define XMT_LOWER_LIMIT_REG_10 0x0b 219 #define XMT_UPPER_LIMIT_REG_10 0x0a 220 static unsigned xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO; 221 static unsigned xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO; 222 223 /* Bank 2 registers */ 224 #define XMT_Chain_Int 0x20 /* Interrupt at the end of the transmit chain */ 225 #define XMT_Chain_ErrStop 0x40 /* Interrupt at the end of the chain even if there are errors */ 226 #define RCV_Discard_BadFrame 0x80 /* Throw bad frames away, and continue to receive others */ 227 #define REG2 0x02 228 #define PRMSC_Mode 0x01 229 #define Multi_IA 0x20 230 #define REG3 0x03 231 #define TPE_BIT 0x04 232 #define BNC_BIT 0x20 233 #define REG13 0x0d 234 #define FDX 0x00 235 #define A_N_ENABLE 0x02 236 237 #define I_ADD_REG0 0x04 238 #define I_ADD_REG1 0x05 239 #define I_ADD_REG2 0x06 240 #define I_ADD_REG3 0x07 241 #define I_ADD_REG4 0x08 242 #define I_ADD_REG5 0x09 243 244 #define EEPROM_REG_PRO 0x0a 245 #define EEPROM_REG_10 0x0b 246 static unsigned eeprom_reg = EEPROM_REG_PRO; 247 248 #define EESK 0x01 249 #define EECS 0x02 250 #define EEDI 0x04 251 #define EEDO 0x08 252 253 /* The horrible routine to read a word from the serial EEPROM. */ 254 /* IMPORTANT - the 82595 will be set to Bank 0 after the eeprom is read */ 255 256 /* The delay between EEPROM clock transitions. */ 257 #define eeprom_delay() { udelay(40); } 258 #define EE_READ_CMD (6 << 6) 259 260 /* do a full reset */ 261 #define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(40); 262 263 /* do a nice reset */ 264 #define eepro_sel_reset(ioaddr) { \ 265 outb(SEL_RESET_CMD, ioaddr); \ 266 SLOW_DOWN; \ 267 SLOW_DOWN; \ 268 } 269 270 /* clear all interrupts */ 271 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG) 272 273 /* enable rx */ 274 #define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr) 275 276 /* disable rx */ 277 #define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr) 278 279 /* switch bank */ 280 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr) 281 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr) 282 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr) 283 284 static unsigned int rx_start, tx_start; 285 static int tx_last; 286 static unsigned tx_end; 287 static int eepro = 0; 288 static unsigned short ioaddr = 0; 289 static unsigned int mem_start, mem_end = RCV_DEFAULT_RAM / 1024; 290 291 #define udelay(n) waiton_timer2(((n)*TICKS_PER_MS)/1000) 292 293 /************************************************************************** 294 RESET - Reset adapter 295 ***************************************************************************/ 296 static void eepro_reset(struct nic *nic) 297 { 298 int temp_reg, i; 299 300 /* put the card in its initial state */ 301 eepro_sw2bank2(ioaddr); /* be careful, bank2 now */ 302 temp_reg = inb(ioaddr + eeprom_reg); 303 #ifdef DEBUG 304 printf("Stepping %d\n", temp_reg >> 5); 305 #endif 306 if (temp_reg & 0x10) /* check the TurnOff Enable bit */ 307 outb(temp_reg & 0xEF, ioaddr + eeprom_reg); 308 for (i = 0; i < ETH_ALEN; i++) /* fill the MAC address */ 309 outb(nic->node_addr[i], ioaddr + I_ADD_REG0 + i); 310 temp_reg = inb(ioaddr + REG1); 311 /* setup Transmit Chaining and discard bad RCV frames */ 312 outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop 313 | RCV_Discard_BadFrame, ioaddr + REG1); 314 temp_reg = inb(ioaddr + REG2); /* match broadcast */ 315 outb(temp_reg | 0x14, ioaddr + REG2); 316 temp_reg = inb(ioaddr + REG3); 317 outb(temp_reg & 0x3F, ioaddr + REG3); /* clear test mode */ 318 /* set the receiving mode */ 319 eepro_sw2bank1(ioaddr); /* be careful, bank1 now */ 320 /* initialise the RCV and XMT upper and lower limits */ 321 outb(RCV_LOWER_LIMIT, ioaddr + RCV_LOWER_LIMIT_REG); 322 outb(RCV_UPPER_LIMIT, ioaddr + RCV_UPPER_LIMIT_REG); 323 outb(XMT_LOWER_LIMIT, ioaddr + xmt_lower_limit_reg); 324 outb(XMT_UPPER_LIMIT, ioaddr + xmt_upper_limit_reg); 325 eepro_sw2bank0(ioaddr); /* Switch back to bank 0 */ 326 eepro_clear_int(ioaddr); 327 /* Initialise RCV */ 328 outw(rx_start = (RCV_LOWER_LIMIT << 8), ioaddr + RCV_BAR); 329 outw(((RCV_UPPER_LIMIT << 8) | 0xFE), ioaddr + RCV_STOP); 330 /* Intialise XMT */ 331 outw((XMT_LOWER_LIMIT << 8), ioaddr + xmt_bar); 332 eepro_sel_reset(ioaddr); 333 tx_start = tx_end = (XMT_LOWER_LIMIT << 8); 334 tx_last = 0; 335 eepro_en_rx(ioaddr); 336 } 337 338 /************************************************************************** 339 POLL - Wait for a frame 340 ***************************************************************************/ 341 static int eepro_poll(struct nic *nic) 342 { 343 int i; 344 unsigned int rcv_car = rx_start; 345 unsigned int rcv_event, rcv_status, rcv_next_frame, rcv_size; 346 347 /* return true if there's an ethernet packet ready to read */ 348 /* nic->packet should contain data on return */ 349 /* nic->packetlen should contain length of data */ 350 #if 0 351 if ((inb(ioaddr + STATUS_REG) & 0x40) == 0) 352 return (0); 353 outb(0x40, ioaddr + STATUS_REG); 354 #endif 355 outw(rcv_car, ioaddr + HOST_ADDRESS_REG); 356 rcv_event = inw(ioaddr + IO_PORT); 357 if (rcv_event != RCV_DONE) 358 return (0); 359 rcv_status = inw(ioaddr + IO_PORT); 360 rcv_next_frame = inw(ioaddr + IO_PORT); 361 rcv_size = inw(ioaddr + IO_PORT); 362 #if 0 363 printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size, 364 inb(ioaddr + STATUS_REG)); 365 #endif 366 if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) { 367 printf("Receive error %hX\n", rcv_status); 368 return (0); 369 } 370 rcv_size &= 0x3FFF; 371 insw(ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1)); 372 #if 0 373 for (i = 0; i < 48; i++) { 374 printf("%hhX", nic->packet[i]); 375 putchar(i % 16 == 15 ? '\n' : ' '); 376 } 377 #endif 378 nic->packetlen = rcv_size; 379 rcv_car = rx_start + RCV_HEADER + rcv_size; 380 rx_start = rcv_next_frame; 381 if (rcv_car == 0) 382 rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff); 383 outw(rcv_car - 1, ioaddr + RCV_STOP); 384 return (1); 385 } 386 387 /************************************************************************** 388 TRANSMIT - Transmit a frame 389 ***************************************************************************/ 390 static void eepro_transmit( 391 struct nic *nic, 392 const char *d, /* Destination */ 393 unsigned int t, /* Type */ 394 unsigned int s, /* size */ 395 const char *p) /* Packet */ 396 { 397 unsigned int status, tx_available, last, end, length; 398 unsigned short type; 399 int boguscount = 20; 400 401 length = s + ETH_HLEN; 402 if (tx_end > tx_start) 403 tx_available = XMT_RAM - (tx_end - tx_start); 404 else if (tx_end < tx_start) 405 tx_available = tx_start - tx_end; 406 else 407 tx_available = XMT_RAM; 408 last = tx_end; 409 end = last + (((length + 3) >> 1) << 1) + XMT_HEADER; 410 if (end >= (XMT_UPPER_LIMIT << 8)) { 411 last = (XMT_LOWER_LIMIT << 8); 412 end = last + (((length + 3) >> 1) << 1) + XMT_HEADER; 413 } 414 outw(last, ioaddr + HOST_ADDRESS_REG); 415 outw(XMT_CMD, ioaddr + IO_PORT); 416 outw(0, ioaddr + IO_PORT); 417 outw(end, ioaddr + IO_PORT); 418 outw(length, ioaddr + IO_PORT); 419 outsw(ioaddr + IO_PORT, d, ETH_ALEN / 2); 420 outsw(ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2); 421 type = htons(t); 422 outsw(ioaddr + IO_PORT, &type, sizeof(type) / 2); 423 outsw(ioaddr + IO_PORT, p, (s + 3) >> 1); 424 /* A dummy read to flush the DRAM write pipeline */ 425 status = inw(ioaddr + IO_PORT); 426 outw(last, ioaddr + xmt_bar); 427 outb(XMT_CMD, ioaddr); 428 tx_start = last; 429 tx_last = last; 430 tx_end = end; 431 #if 0 432 printf("%d %d\n", tx_start, tx_end); 433 #endif 434 while (boguscount > 0) { 435 if (((status = inw(ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) { 436 udelay(40); 437 boguscount--; 438 continue; 439 } 440 #if DEBUG 441 if ((status & 0x2000) == 0) 442 printf("Transmit status %hX\n", status); 443 #endif 444 } 445 } 446 447 /************************************************************************** 448 DISABLE - Turn off ethernet interface 449 ***************************************************************************/ 450 static void eepro_disable(struct nic *nic) 451 { 452 eepro_sw2bank0(ioaddr); /* Switch to bank 0 */ 453 /* Flush the Tx and disable Rx */ 454 outb(STOP_RCV_CMD, ioaddr); 455 tx_start = tx_end = (XMT_LOWER_LIMIT << 8); 456 tx_last = 0; 457 /* Reset the 82595 */ 458 eepro_full_reset(ioaddr); 459 } 460 461 static int read_eeprom(int location) 462 { 463 int i; 464 unsigned short retval = 0; 465 int ee_addr = ioaddr + eeprom_reg; 466 int read_cmd = location | EE_READ_CMD; 467 int ctrl_val = EECS; 468 469 if (eepro == LAN595FX_10ISA) { 470 eepro_sw2bank1(ioaddr); 471 outb(0x00, ioaddr + STATUS_REG); 472 } 473 eepro_sw2bank2(ioaddr); 474 outb(ctrl_val, ee_addr); 475 /* shift the read command bits out */ 476 for (i = 8; i >= 0; i--) { 477 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val; 478 outb(outval, ee_addr); 479 outb(outval | EESK, ee_addr); /* EEPROM clock tick */ 480 eeprom_delay(); 481 outb(outval, ee_addr); /* finish EEPROM clock tick */ 482 eeprom_delay(); 483 } 484 outb(ctrl_val, ee_addr); 485 for (i = 16; i > 0; i--) { 486 outb(ctrl_val | EESK, ee_addr); 487 eeprom_delay(); 488 retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0); 489 outb(ctrl_val, ee_addr); 490 eeprom_delay(); 491 } 492 /* terminate the EEPROM access */ 493 ctrl_val &= ~EECS; 494 outb(ctrl_val | EESK, ee_addr); 495 eeprom_delay(); 496 outb(ctrl_val, ee_addr); 497 eeprom_delay(); 498 eepro_sw2bank0(ioaddr); 499 return (retval); 500 } 501 502 static int eepro_probe1(struct nic *nic) 503 { 504 int i, id, counter, l_eepro = 0; 505 union { 506 unsigned char caddr[ETH_ALEN]; 507 unsigned short saddr[ETH_ALEN/2]; 508 } station_addr; 509 char *name; 510 511 id = inb(ioaddr + ID_REG); 512 if ((id & ID_REG_MASK) != ID_REG_SIG) 513 return (0); 514 counter = id & R_ROBIN_BITS; 515 if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40)) 516 return (0); 517 /* yes the 82595 has been found */ 518 station_addr.saddr[2] = read_eeprom(2); 519 if (station_addr.saddr[2] == 0x0000 || station_addr.saddr[2] == 0xFFFF) { 520 l_eepro = 3; 521 eepro = LAN595FX_10ISA; 522 eeprom_reg= EEPROM_REG_10; 523 rcv_start = RCV_START_10; 524 xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10; 525 xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10; 526 station_addr.saddr[2] = read_eeprom(2); 527 } 528 station_addr.saddr[1] = read_eeprom(3); 529 station_addr.saddr[0] = read_eeprom(4); 530 if (l_eepro) 531 name = "Intel EtherExpress 10 ISA"; 532 else if (read_eeprom(7) == ee_FX_INT2IRQ) { 533 name = "Intel EtherExpress Pro/10+ ISA"; 534 l_eepro = 2; 535 } else if (station_addr.saddr[0] == SA_ADDR1) { 536 name = "Intel EtherExpress Pro/10 ISA"; 537 l_eepro = 1; 538 } else { 539 l_eepro = 0; 540 name = "Intel 82595-based LAN card"; 541 } 542 station_addr.saddr[0] = swap16(station_addr.saddr[0]); 543 station_addr.saddr[1] = swap16(station_addr.saddr[1]); 544 station_addr.saddr[2] = swap16(station_addr.saddr[2]); 545 for (i = 0; i < ETH_ALEN; i++) { 546 nic->node_addr[i] = station_addr.caddr[i]; 547 } 548 printf("\n%s ioaddr %#hX, addr %!", name, ioaddr, nic->node_addr); 549 mem_start = RCV_LOWER_LIMIT << 8; 550 if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29) 551 mem_end = RCV_UPPER_LIMIT << 8; 552 else { 553 mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8); 554 rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8); 555 } 556 printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10, 557 GetBit(read_eeprom(5), ee_BNC_TPE) ? "BNC" : "TP"); 558 return (1); 559 } 560 561 /************************************************************************** 562 PROBE - Look for an adapter, this routine's visible to the outside 563 ***************************************************************************/ 564 struct nic *eepro_probe(struct nic *nic, unsigned short *probe_addrs) 565 { 566 unsigned short *p; 567 /* same probe list as the Linux driver */ 568 static unsigned short ioaddrs[] = { 569 0x300, 0x210, 0x240, 0x280, 0x2C0, 0x200, 0x320, 0x340, 0x360, 0}; 570 571 if (probe_addrs == 0 || probe_addrs[0] == 0) 572 probe_addrs = ioaddrs; 573 for (p = probe_addrs; (ioaddr = *p) != 0; p++) { 574 if (eepro_probe1(nic)) 575 break; 576 } 577 if (*p == 0) 578 return (0); 579 eepro_reset(nic); 580 /* point to NIC specific routines */ 581 nic->reset = eepro_reset; 582 nic->poll = eepro_poll; 583 nic->transmit = eepro_transmit; 584 nic->disable = eepro_disable; 585 return (nic); 586 } 587
