1 /* 2 * QEMU 8259 interrupt controller emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw.h" 25 #include "pc.h" 26 #include "isa.h" 27 #include "monitor.h" 28 #include "goldfish_device.h" 29 30 /* debug PIC */ 31 //#define DEBUG_PIC 32 33 //#define DEBUG_IRQ_LATENCY 34 //#define DEBUG_IRQ_COUNT 35 36 typedef struct PicState { 37 uint8_t last_irr; /* edge detection */ 38 uint8_t irr; /* interrupt request register */ 39 uint8_t imr; /* interrupt mask register */ 40 uint8_t isr; /* interrupt service register */ 41 uint8_t priority_add; /* highest irq priority */ 42 uint8_t irq_base; 43 uint8_t read_reg_select; 44 uint8_t poll; 45 uint8_t special_mask; 46 uint8_t init_state; 47 uint8_t auto_eoi; 48 uint8_t rotate_on_auto_eoi; 49 uint8_t special_fully_nested_mode; 50 uint8_t init4; /* true if 4 byte init */ 51 uint8_t single_mode; /* true if slave pic is not initialized */ 52 uint8_t elcr; /* PIIX edge/trigger selection*/ 53 uint8_t elcr_mask; 54 PicState2 *pics_state; 55 } PicState; 56 57 struct PicState2 { 58 /* 0 is master pic, 1 is slave pic */ 59 /* XXX: better separation between the two pics */ 60 PicState pics[2]; 61 qemu_irq parent_irq; 62 void *irq_request_opaque; 63 /* IOAPIC callback support */ 64 SetIRQFunc *alt_irq_func; 65 void *alt_irq_opaque; 66 }; 67 68 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT) 69 static int irq_level[16]; 70 #endif 71 #ifdef DEBUG_IRQ_COUNT 72 static uint64_t irq_count[16]; 73 #endif 74 75 /* set irq level. If an edge is detected, then the IRR is set to 1 */ 76 static inline void pic_set_irq1(PicState *s, int irq, int level) 77 { 78 int mask; 79 mask = 1 << irq; 80 if (s->elcr & mask) { 81 /* level triggered */ 82 if (level) { 83 s->irr |= mask; 84 s->last_irr |= mask; 85 } else { 86 s->irr &= ~mask; 87 s->last_irr &= ~mask; 88 } 89 } else { 90 /* edge triggered */ 91 if (level) { 92 if ((s->last_irr & mask) == 0) 93 s->irr |= mask; 94 s->last_irr |= mask; 95 } else { 96 s->last_irr &= ~mask; 97 } 98 } 99 } 100 101 /* return the highest priority found in mask (highest = smallest 102 number). Return 8 if no irq */ 103 static inline int get_priority(PicState *s, int mask) 104 { 105 int priority; 106 if (mask == 0) 107 return 8; 108 priority = 0; 109 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) 110 priority++; 111 return priority; 112 } 113 114 /* return the pic wanted interrupt. return -1 if none */ 115 static int pic_get_irq(PicState *s) 116 { 117 int mask, cur_priority, priority; 118 119 mask = s->irr & ~s->imr; 120 priority = get_priority(s, mask); 121 if (priority == 8) 122 return -1; 123 /* compute current priority. If special fully nested mode on the 124 master, the IRQ coming from the slave is not taken into account 125 for the priority computation. */ 126 mask = s->isr; 127 if (s->special_mask) 128 mask &= ~s->imr; 129 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) 130 mask &= ~(1 << 2); 131 cur_priority = get_priority(s, mask); 132 if (priority < cur_priority) { 133 /* higher priority found: an irq should be generated */ 134 return (priority + s->priority_add) & 7; 135 } else { 136 return -1; 137 } 138 } 139 140 /* raise irq to CPU if necessary. must be called every time the active 141 irq may change */ 142 /* XXX: should not export it, but it is needed for an APIC kludge */ 143 void pic_update_irq(PicState2 *s) 144 { 145 int irq2, irq; 146 147 /* first look at slave pic */ 148 irq2 = pic_get_irq(&s->pics[1]); 149 if (irq2 >= 0) { 150 /* if irq request by slave pic, signal master PIC */ 151 pic_set_irq1(&s->pics[0], 2, 1); 152 pic_set_irq1(&s->pics[0], 2, 0); 153 } 154 /* look at requested irq */ 155 irq = pic_get_irq(&s->pics[0]); 156 if (irq >= 0) { 157 #if defined(DEBUG_PIC) 158 { 159 int i; 160 for(i = 0; i < 2; i++) { 161 printf("pic%d: imr=%x irr=%x padd=%d\n", 162 i, s->pics[i].imr, s->pics[i].irr, 163 s->pics[i].priority_add); 164 165 } 166 } 167 printf("pic: cpu_interrupt\n"); 168 #endif 169 qemu_irq_raise(s->parent_irq); 170 } 171 172 /* all targets should do this rather than acking the IRQ in the cpu */ 173 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA) 174 else { 175 qemu_irq_lower(s->parent_irq); 176 } 177 #endif 178 } 179 180 #ifdef DEBUG_IRQ_LATENCY 181 int64_t irq_time[16]; 182 #endif 183 184 static void i8259_set_irq(void *opaque, int irq, int level) 185 { 186 PicState2 *s = opaque; 187 188 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) 189 if (level != irq_level[irq]) { 190 #if defined(DEBUG_PIC) 191 printf("i8259_set_irq: irq=%d level=%d\n", irq, level); 192 #endif 193 irq_level[irq] = level; 194 #ifdef DEBUG_IRQ_COUNT 195 if (level == 1) 196 irq_count[irq]++; 197 #endif 198 } 199 #endif 200 #ifdef DEBUG_IRQ_LATENCY 201 if (level) { 202 irq_time[irq] = qemu_get_clock(vm_clock); 203 } 204 #endif 205 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); 206 /* used for IOAPIC irqs */ 207 if (s->alt_irq_func) 208 s->alt_irq_func(s->alt_irq_opaque, irq, level); 209 pic_update_irq(s); 210 } 211 212 /* acknowledge interrupt 'irq' */ 213 static inline void pic_intack(PicState *s, int irq) 214 { 215 if (s->auto_eoi) { 216 if (s->rotate_on_auto_eoi) 217 s->priority_add = (irq + 1) & 7; 218 } else { 219 s->isr |= (1 << irq); 220 } 221 /* We don't clear a level sensitive interrupt here */ 222 if (!(s->elcr & (1 << irq))) 223 s->irr &= ~(1 << irq); 224 } 225 226 int pic_read_irq(PicState2 *s) 227 { 228 int irq, irq2, intno; 229 230 irq = pic_get_irq(&s->pics[0]); 231 if (irq >= 0) { 232 pic_intack(&s->pics[0], irq); 233 if (irq == 2) { 234 irq2 = pic_get_irq(&s->pics[1]); 235 if (irq2 >= 0) { 236 pic_intack(&s->pics[1], irq2); 237 } else { 238 /* spurious IRQ on slave controller */ 239 irq2 = 7; 240 } 241 intno = s->pics[1].irq_base + irq2; 242 irq = irq2 + 8; 243 } else { 244 intno = s->pics[0].irq_base + irq; 245 } 246 } else { 247 /* spurious IRQ on host controller */ 248 irq = 7; 249 intno = s->pics[0].irq_base + irq; 250 } 251 pic_update_irq(s); 252 253 #ifdef DEBUG_IRQ_LATENCY 254 printf("IRQ%d latency=%0.3fus\n", 255 irq, 256 (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / get_ticks_per_sec); 257 #endif 258 #if defined(DEBUG_PIC) 259 printf("pic_interrupt: irq=%d\n", irq); 260 #endif 261 return intno; 262 } 263 264 static void pic_reset(void *opaque) 265 { 266 PicState *s = opaque; 267 268 s->last_irr = 0; 269 s->irr = 0; 270 s->imr = 0; 271 s->isr = 0; 272 s->priority_add = 0; 273 s->irq_base = 0; 274 s->read_reg_select = 0; 275 s->poll = 0; 276 s->special_mask = 0; 277 s->init_state = 0; 278 s->auto_eoi = 0; 279 s->rotate_on_auto_eoi = 0; 280 s->special_fully_nested_mode = 0; 281 s->init4 = 0; 282 s->single_mode = 0; 283 /* Note: ELCR is not reset */ 284 } 285 286 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) 287 { 288 PicState *s = opaque; 289 int priority, cmd, irq; 290 291 #ifdef DEBUG_PIC 292 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val); 293 #endif 294 addr &= 1; 295 if (addr == 0) { 296 if (val & 0x10) { 297 /* init */ 298 pic_reset(s); 299 /* deassert a pending interrupt */ 300 qemu_irq_lower(s->pics_state->parent_irq); 301 s->init_state = 1; 302 s->init4 = val & 1; 303 s->single_mode = val & 2; 304 if (val & 0x08) 305 hw_error("level sensitive irq not supported"); 306 } else if (val & 0x08) { 307 if (val & 0x04) 308 s->poll = 1; 309 if (val & 0x02) 310 s->read_reg_select = val & 1; 311 if (val & 0x40) 312 s->special_mask = (val >> 5) & 1; 313 } else { 314 cmd = val >> 5; 315 switch(cmd) { 316 case 0: 317 case 4: 318 s->rotate_on_auto_eoi = cmd >> 2; 319 break; 320 case 1: /* end of interrupt */ 321 case 5: 322 priority = get_priority(s, s->isr); 323 if (priority != 8) { 324 irq = (priority + s->priority_add) & 7; 325 s->isr &= ~(1 << irq); 326 if (cmd == 5) 327 s->priority_add = (irq + 1) & 7; 328 pic_update_irq(s->pics_state); 329 } 330 break; 331 case 3: 332 irq = val & 7; 333 s->isr &= ~(1 << irq); 334 pic_update_irq(s->pics_state); 335 break; 336 case 6: 337 s->priority_add = (val + 1) & 7; 338 pic_update_irq(s->pics_state); 339 break; 340 case 7: 341 irq = val & 7; 342 s->isr &= ~(1 << irq); 343 s->priority_add = (irq + 1) & 7; 344 pic_update_irq(s->pics_state); 345 break; 346 default: 347 /* no operation */ 348 break; 349 } 350 } 351 } else { 352 switch(s->init_state) { 353 case 0: 354 /* normal mode */ 355 s->imr = val; 356 pic_update_irq(s->pics_state); 357 break; 358 case 1: 359 s->irq_base = val & 0xf8; 360 s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2; 361 break; 362 case 2: 363 if (s->init4) { 364 s->init_state = 3; 365 } else { 366 s->init_state = 0; 367 } 368 break; 369 case 3: 370 s->special_fully_nested_mode = (val >> 4) & 1; 371 s->auto_eoi = (val >> 1) & 1; 372 s->init_state = 0; 373 break; 374 } 375 } 376 } 377 378 static uint32_t pic_poll_read (PicState *s, uint32_t addr1) 379 { 380 int ret; 381 382 ret = pic_get_irq(s); 383 if (ret >= 0) { 384 if (addr1 >> 7) { 385 s->pics_state->pics[0].isr &= ~(1 << 2); 386 s->pics_state->pics[0].irr &= ~(1 << 2); 387 } 388 s->irr &= ~(1 << ret); 389 s->isr &= ~(1 << ret); 390 if (addr1 >> 7 || ret != 2) 391 pic_update_irq(s->pics_state); 392 } else { 393 ret = 0x07; 394 pic_update_irq(s->pics_state); 395 } 396 397 return ret; 398 } 399 400 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) 401 { 402 PicState *s = opaque; 403 unsigned int addr; 404 int ret; 405 406 addr = addr1; 407 addr &= 1; 408 if (s->poll) { 409 ret = pic_poll_read(s, addr1); 410 s->poll = 0; 411 } else { 412 if (addr == 0) { 413 if (s->read_reg_select) 414 ret = s->isr; 415 else 416 ret = s->irr; 417 } else { 418 ret = s->imr; 419 } 420 } 421 #ifdef DEBUG_PIC 422 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret); 423 #endif 424 return ret; 425 } 426 427 /* memory mapped interrupt status */ 428 /* XXX: may be the same than pic_read_irq() */ 429 uint32_t pic_intack_read(PicState2 *s) 430 { 431 int ret; 432 433 ret = pic_poll_read(&s->pics[0], 0x00); 434 if (ret == 2) 435 ret = pic_poll_read(&s->pics[1], 0x80) + 8; 436 /* Prepare for ISR read */ 437 s->pics[0].read_reg_select = 1; 438 439 return ret; 440 } 441 442 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val) 443 { 444 PicState *s = opaque; 445 s->elcr = val & s->elcr_mask; 446 } 447 448 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1) 449 { 450 PicState *s = opaque; 451 return s->elcr; 452 } 453 454 static void pic_save(QEMUFile *f, void *opaque) 455 { 456 PicState *s = opaque; 457 458 qemu_put_8s(f, &s->last_irr); 459 qemu_put_8s(f, &s->irr); 460 qemu_put_8s(f, &s->imr); 461 qemu_put_8s(f, &s->isr); 462 qemu_put_8s(f, &s->priority_add); 463 qemu_put_8s(f, &s->irq_base); 464 qemu_put_8s(f, &s->read_reg_select); 465 qemu_put_8s(f, &s->poll); 466 qemu_put_8s(f, &s->special_mask); 467 qemu_put_8s(f, &s->init_state); 468 qemu_put_8s(f, &s->auto_eoi); 469 qemu_put_8s(f, &s->rotate_on_auto_eoi); 470 qemu_put_8s(f, &s->special_fully_nested_mode); 471 qemu_put_8s(f, &s->init4); 472 qemu_put_8s(f, &s->single_mode); 473 qemu_put_8s(f, &s->elcr); 474 } 475 476 static int pic_load(QEMUFile *f, void *opaque, int version_id) 477 { 478 PicState *s = opaque; 479 480 if (version_id != 1) 481 return -EINVAL; 482 483 qemu_get_8s(f, &s->last_irr); 484 qemu_get_8s(f, &s->irr); 485 qemu_get_8s(f, &s->imr); 486 qemu_get_8s(f, &s->isr); 487 qemu_get_8s(f, &s->priority_add); 488 qemu_get_8s(f, &s->irq_base); 489 qemu_get_8s(f, &s->read_reg_select); 490 qemu_get_8s(f, &s->poll); 491 qemu_get_8s(f, &s->special_mask); 492 qemu_get_8s(f, &s->init_state); 493 qemu_get_8s(f, &s->auto_eoi); 494 qemu_get_8s(f, &s->rotate_on_auto_eoi); 495 qemu_get_8s(f, &s->special_fully_nested_mode); 496 qemu_get_8s(f, &s->init4); 497 qemu_get_8s(f, &s->single_mode); 498 qemu_get_8s(f, &s->elcr); 499 return 0; 500 } 501 502 /* XXX: add generic master/slave system */ 503 static void pic_init1(int io_addr, int elcr_addr, PicState *s) 504 { 505 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s); 506 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s); 507 if (elcr_addr >= 0) { 508 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s); 509 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s); 510 } 511 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s); 512 qemu_register_reset(pic_reset, 0, s); 513 } 514 515 void pic_info(Monitor *mon) 516 { 517 int i; 518 PicState *s; 519 520 if (!isa_pic) 521 return; 522 523 for(i=0;i<2;i++) { 524 s = &isa_pic->pics[i]; 525 monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " 526 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", 527 i, s->irr, s->imr, s->isr, s->priority_add, 528 s->irq_base, s->read_reg_select, s->elcr, 529 s->special_fully_nested_mode); 530 } 531 } 532 533 void irq_info(Monitor *mon) 534 { 535 #ifndef DEBUG_IRQ_COUNT 536 monitor_printf(mon, "irq statistic code not compiled.\n"); 537 #else 538 int i; 539 int64_t count; 540 541 monitor_printf(mon, "IRQ statistics:\n"); 542 for (i = 0; i < 16; i++) { 543 count = irq_count[i]; 544 if (count > 0) 545 monitor_printf(mon, "%2d: %" PRId64 "\n", i, count); 546 } 547 #endif 548 } 549 550 qemu_irq *i8259_init(qemu_irq parent_irq) 551 { 552 PicState2 *s; 553 554 s = qemu_mallocz(sizeof(PicState2)); 555 pic_init1(0x20, 0x4d0, &s->pics[0]); 556 pic_init1(0xa0, 0x4d1, &s->pics[1]); 557 s->pics[0].elcr_mask = 0xf8; 558 s->pics[1].elcr_mask = 0xde; 559 s->parent_irq = parent_irq; 560 s->pics[0].pics_state = s; 561 s->pics[1].pics_state = s; 562 isa_pic = s; 563 return qemu_allocate_irqs(i8259_set_irq, s, GFD_MAX_IRQ); 564 } 565 566 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func, 567 void *alt_irq_opaque) 568 { 569 s->alt_irq_func = alt_irq_func; 570 s->alt_irq_opaque = alt_irq_opaque; 571 } 572
