| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 210 case ISD::ADDE: {
213 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
218 if (Opcode == ISD::ADDE) {
|
| MipsISelLowering.cpp | 217 setTargetDAGCombine(ISD::ADDE);
245 // (addc multLo, Lo0), (adde multHi, Hi0),
307 // replace uses of adde and addc here
644 case ISD::ADDE:
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 217 ADDE, SUBE,
[all...] |
| SelectionDAG.h | [all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 98 setOperationAction(ISD::ADDE, MVT::i32, Custom);
422 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
429 unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
471 case ISD::ADDE:
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 75 ADDE, // Add using carry
|
| ARMISelLowering.cpp | 569 setOperationAction(ISD::ADDE, MVT::i32, Custom);
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 346 #define ADDE XO31(138)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 103 setOperationAction(ISD::ADDE , MVT::i64, Expand);
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 336 #define ADDE XO31(138)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 317 case ISD::ADDE:
[all...] |
| X86ISelLowering.cpp | 362 setOperationAction(ISD::ADDE, VT, Custom);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 90 setOperationAction(ISD::ADDE, MVT::i32, Expand);
[all...] |
