/external/v8/src/mips/ |
constants-mips.cc | 304 // 16 bits Immediate type instructions. eg: addi dest, src, imm16 310 case ADDI:
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constants-mips.h | 209 ADDI = ((1 << 3) + 0) << kOpcodeShift,
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assembler-mips.cc | [all...] |
simulator-mips.cc | [all...] |
/external/qemu/tcg/ppc/ |
tcg-target.c | 315 #define ADDI OPCD(14) 449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); 695 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4); 701 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4); 881 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4); 888 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4); 955 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size); 977 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff)); 981 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff)); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 83 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 290 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 335 /// addi R0, SP, \#frameSize ; get the address of the previous frame 337 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 367 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 382 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 431 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 436 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 612 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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PPCFrameLowering.cpp | 587 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 602 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 667 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; [all...] |
PPCInstrInfo.cpp | 461 // R0 = ADDI FI# 465 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0), 590 // R0 = ADDI FI# 594 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
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PPCISelDAGToDAG.cpp | 671 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op, 827 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8; [all...] |
/external/qemu/tcg/ppc64/ |
tcg-target.c | 303 #define ADDI OPCD( 14) 453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff)); 741 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4); 850 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4); 923 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size); 951 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff)); 955 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff)); [all...] |
/external/llvm/lib/Target/MBlaze/Disassembler/ |
MBlazeDisassembler.cpp | 43 MBlaze::ADDI, MBlaze::RSUBI, MBlaze::ADDIC, MBlaze::RSUBIC, //08,09,0A,0B
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