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    Searched refs:BaseReg (Results 1 - 25 of 26) sorted by null

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  /external/llvm/include/llvm/Transforms/Utils/
AddrModeMatcher.h 37 Value *BaseReg;
39 ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
44 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
  /external/llvm/lib/Target/X86/InstPrinter/
X86ATTInstPrinter.cpp 110 const MCOperand &BaseReg = MI->getOperand(Op);
123 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
130 if (IndexReg.getReg() || BaseReg.getReg()) {
132 if (BaseReg.getReg())
X86IntelInstPrinter.cpp 97 const MCOperand &BaseReg = MI->getOperand(Op);
112 if (BaseReg.getReg()) {
132 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
  /external/llvm/lib/CodeGen/
LocalStackSlotAllocation.cpp 294 unsigned BaseReg = 0;
314 BaseReg = RegOffset.first;
322 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
324 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
331 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
342 std::pair<unsigned, int64_t>(BaseReg, BaseOffset));
346 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
350 TRI->resolveFrameIndex(I, BaseReg, Offset);
  /external/llvm/lib/Transforms/Utils/
AddrModeMatcher.cpp 42 if (BaseReg) {
45 WriteAsOperand(OS, BaseReg, /*PrintType=*/false);
275 AddrMode.BaseReg = AddrInst->getOperand(0);
288 AddrMode.BaseReg = AddrInst->getOperand(0);
356 AddrMode.BaseReg = Addr;
361 AddrMode.BaseReg = 0;
521 // BaseReg and ScaleReg (global addresses are always available, as are any
523 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg;
525 // If the BaseReg or ScaledReg was referenced by the previous addrmode, thei
    [all...]
  /external/llvm/lib/Target/ARM/
Thumb1RegisterInfo.cpp 85 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
92 unsigned DestReg, unsigned BaseReg,
99 (BaseReg != 0 && !isARMLowRegister(BaseReg));
111 assert(BaseReg == ARM::SP && "Unexpected!");
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
165 /// a destreg = basereg + immediate in Thumb code.
169 unsigned DestReg, unsigned BaseReg,
185 if (DestReg == BaseReg && BaseReg == ARM::SP)
    [all...]
Thumb2InstrInfo.cpp 176 unsigned DestReg, unsigned BaseReg, int NumBytes,
184 if (DestReg != ARM::SP && DestReg != BaseReg &&
206 .addReg(BaseReg, RegState::Kill)
213 .addReg(BaseReg, RegState::Kill)
224 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
227 .addReg(BaseReg).setMIFlags(MIFlags));
228 BaseReg = ARM::SP;
233 if (BaseReg == ARM::SP) {
239 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
257 assert(DestReg != ARM::SP && BaseReg != ARM::SP)
    [all...]
Thumb1RegisterInfo.h 58 unsigned BaseReg, int64_t Offset) const;
ARMBaseRegisterInfo.h 147 unsigned BaseReg, int FrameIdx,
150 unsigned BaseReg, int64_t Offset) const;
ARMBaseInstrInfo.h 349 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
353 unsigned DestReg, unsigned BaseReg, int NumBytes,
359 unsigned DestReg, unsigned BaseReg, int NumBytes,
364 unsigned DestReg, unsigned BaseReg,
Thumb2SizeReduction.cpp 126 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
369 unsigned BaseReg = MI->getOperand(0).getReg();
370 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
377 if (MI->getOperand(i).getReg() == BaseReg) {
391 unsigned BaseReg = MI->getOperand(1).getReg();
392 if (BaseReg != ARM::SP)
405 unsigned BaseReg = MI->getOperand(1).getReg();
406 if (BaseReg == ARM::SP &&
411 } else if (!isARMLowRegister(BaseReg) ||
ARMLoadStoreOptimizer.cpp     [all...]
ARMBaseRegisterInfo.cpp     [all...]
ARMConstantIslandPass.cpp     [all...]
ARMBaseInstrInfo.cpp 155 unsigned BaseReg = Base.getReg();
173 .addReg(BaseReg).addImm(Amt)
180 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
185 .addReg(BaseReg).addReg(OffReg)
196 .addReg(BaseReg).addImm(Amt)
201 .addReg(BaseReg).addReg(OffReg)
223 .addReg(BaseReg).addImm(0).addImm(Pred);
227 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
    [all...]
ARMISelDAGToDAG.cpp 174 SDValue &BaseReg, SDValue &Opc);
391 SDValue &BaseReg,
403 BaseReg = N.getOperand(0);
414 SDValue &BaseReg,
427 BaseReg = N.getOperand(0);
    [all...]
  /external/llvm/lib/Target/Blackfin/
BlackfinRegisterInfo.cpp 207 unsigned BaseReg = BF::FP;
211 BaseReg = BF::SP;
223 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
231 if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
258 MI.getOperand(2).ChangeToRegister(BaseReg, false);
272 .addReg(BaseReg);
296 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
308 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
  /external/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 138 unsigned BaseReg;
186 return Mem.BaseReg;
350 Res->Mem.BaseReg = 0;
358 unsigned BaseReg, unsigned IndexReg,
362 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
370 Res->Mem.BaseReg = BaseReg;
380 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; local
386 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0)
390 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; local
    [all...]
  /external/llvm/lib/Target/X86/
X86CodeEmitter.cpp 471 unsigned BaseReg = Base.getReg();
474 if (BaseReg == X86::RIP ||
489 // If no BaseReg, issue a RIP relative instruction only if the MCE can
493 if (BaseReg != 0 && BaseReg != X86::RIP)
494 BaseRegNo = X86_MC::getX86RegNum(BaseReg);
504 (!Is64BitMode || BaseReg != 0)) {
505 if (BaseReg == 0 || // [disp32] in X86-32 mode
506 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
540 if (BaseReg == 0)
    [all...]
X86AsmPrinter.cpp 282 const MachineOperand &BaseReg = MI->getOperand(Op);
287 bool HasBaseReg = BaseReg.getReg() != 0;
289 BaseReg.getReg() == X86::RIP)
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 161 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
164 if ((BaseReg.getReg() != 0 &&
165 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
249 unsigned BaseReg = Base.getReg();
252 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
277 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
280 // If no BaseReg, issue a RIP relative instruction only if the MCE can
292 (!is64BitMode() || BaseReg != 0)) {
294 if (BaseReg == 0) { // [disp32] in X86-32 mode
329 if (BaseReg == 0)
    [all...]
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 606 /// BaseReg to be a pointer to FrameIdx before insertion point I.
608 unsigned BaseReg, int FrameIdx,
616 unsigned BaseReg, int64_t Offset) const {
  /external/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 821 const SCEV *BaseReg = *I;
822 if (VisitedRegs.count(BaseReg)) {
826 RatePrimaryRegister(BaseReg, Regs, L, SE, DT);
    [all...]
CodeGenPrepare.cpp 837 if (AddrMode.BaseReg) {
838 Value *V = AddrMode.BaseReg;
    [all...]
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp 169 unsigned BaseReg = MI->getOperand(0).getReg();
171 if (MI->getOperand(i).getReg() == BaseReg)
178 O << '\t' << getRegisterName(BaseReg);

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