| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
330 baseReg = MCOperand::CreateReg(X86::x); break;
335 baseReg = MCOperand::CreateReg(0);
345 indexReg = MCOperand::CreateReg(X86::x); break;
351 indexReg = MCOperand::CreateReg(0);
363 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
365 baseReg = MCOperand::CreateReg(0)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| ARMMCInstLower.cpp | 78 MCOp = MCOperand::CreateReg(MO.getReg());
|
| Thumb2ITBlockPass.cpp | 188 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
213 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
|
| Thumb2InstrInfo.cpp | 429 MI.addOperand(MachineOperand::CreateReg(0, false));
460 MI.addOperand(MachineOperand::CreateReg(0, false));
|
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 538 instr.addOperand(MCOperand::CreateReg(RD));
539 instr.addOperand(MCOperand::CreateReg(RB));
540 instr.addOperand(MCOperand::CreateReg(RA));
546 instr.addOperand(MCOperand::CreateReg(RD));
547 instr.addOperand(MCOperand::CreateReg(RA));
548 instr.addOperand(MCOperand::CreateReg(RB));
558 instr.addOperand(MCOperand::CreateReg(RD));
565 instr.addOperand(MCOperand::CreateReg(RA));
571 instr.addOperand(MCOperand::CreateReg(RD));
580 instr.addOperand(MCOperand::CreateReg(RD))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
81 MO.push_back(MachineOperand::CreateReg(0, false, false,
|
| X86MCInstLower.cpp | 315 MCOp = MCOperand::CreateReg(MO.getReg());
551 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
552 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
554 LEA.addOperand(MCOperand::CreateReg(0)); // index
556 LEA.addOperand(MCOperand::CreateReg(0)); // seg
559 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
560 LEA.addOperand(MCOperand::CreateReg(0)); // base
562 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
564 LEA.addOperand(MCOperand::CreateReg(0)); // seg
656 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg())
[all...] |
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 189 Inst.addOperand(MCOperand::CreateReg(getReg()));
205 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
209 Inst.addOperand(MCOperand::CreateReg(RegOff));
230 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
405 return MBlazeOperand::CreateReg(RegNo, S, E);
|
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 141 unsigned CreateReg(EVT VT);
|
| MachineInstrBuilder.h | 61 MI->addOperand(MachineOperand::CreateReg(RegNo,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430MCInstLower.cpp | 123 MCOp = MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 205 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
220 MI->addOperand(MachineOperand::CreateReg(Reg, true));
232 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
328 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
353 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
514 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
[all...] |
| FunctionLoweringInfo.cpp | 207 /// CreateReg - Allocate a single virtual register for the given type.
208 unsigned FunctionLoweringInfo::CreateReg(EVT VT) {
230 unsigned R = CreateReg(RegisterVT);
|
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
642 MI.insert(I, MCOperand::CreateReg(0));
644 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
652 MI.insert(I, MCOperand::CreateReg(0));
654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 97 static MCOperand CreateReg(unsigned Reg) {
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeMCInstLower.cpp | 129 MCOp = MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/Mips/ |
| MipsMCInstLower.cpp | 101 return MCOperand::CreateReg(MO.getReg());
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 302 Inst.addOperand(MCOperand::CreateReg(getReg()));
312 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
314 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
316 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
332 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
517 return X86Operand::CreateReg(RegNo, Start, End);
806 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
819 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 244 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
256 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
268 LastDef->addOperand(MachineOperand::CreateReg(Reg,
382 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
606 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
|
| ExpandPostRAPseudos.cpp | 96 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
|
| MachineSSAUpdater.cpp | 325 PHI->addOperand(MachineOperand::CreateReg(Val, false));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCMCInstLower.cpp | 146 MCOp = MCOperand::CreateReg(MO.getReg());
|
