| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
48 MachineInstr *DefMI = LastMI;
58 DefMI = &*I;
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 hasRAWHazard(DefMI, MI, TRI))) {
|
| MLxExpansionPass.cpp | 92 MachineInstr *DefMI = MRI->getVRegDef(Reg);
94 if (DefMI->getParent() != MBB)
96 if (DefMI->isCopyLike()) {
97 Reg = DefMI->getOperand(1).getReg();
99 DefMI = MRI->getVRegDef(Reg);
102 } else if (DefMI->isInsertSubreg()) {
103 Reg = DefMI->getOperand(2).getReg();
105 DefMI = MRI->getVRegDef(Reg);
111 return DefMI;
160 MachineInstr *DefMI = getAccDefMI(MI)
[all...] |
| ARMBaseInstrInfo.h | 201 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
209 const MachineInstr *DefMI, unsigned DefIdx,
252 const MachineInstr *DefMI, unsigned DefIdx,
255 const MachineInstr *DefMI, unsigned DefIdx) const;
|
| ARMBaseInstrInfo.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | 56 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
75 MachineInstrBuilder &DefMI) {
84 DefMI.addOperand(MO);
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 45 const MachineInstr *DefMI,
48 assert(DefMI && "Missing instruction");
50 if (!tii.isTriviallyReMaterializable(DefMI, aa))
64 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
65 if (!DefMI)
67 checkRematerializable(VNI, DefMI, tii, aa);
167 MachineInstr *DefMI = 0, *UseMI = 0;
175 if (DefMI && DefMI != MI)
179 DefMI = MI
[all...] |
| PHIElimination.cpp | 134 MachineInstr *DefMI = *I;
135 unsigned DefReg = DefMI->getOperand(0).getReg();
137 DefMI->eraseFromParent();
176 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
177 if (!DefMI || !DefMI->isImplicitDef())
297 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
298 if (DefMI->isImplicitDef()) {
299 ImpDefs.insert(DefMI);
|
| TwoAddressInstructionPass.cpp | 91 MachineInstr *MI, MachineInstr *DefMI,
308 MachineInstr *MI, MachineInstr *DefMI,
334 return MBB == DefMI->getParent();
429 MachineInstr *DefMI = &MI;
431 if (!DefMI->killsRegister(Reg))
440 DefMI = &*Begin;
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| InlineSpiller.cpp | 108 MachineInstr *DefMI;
119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
122 bool hasDef() const { return DefByOrigPHI || DefMI; }
331 if (SVI.DefMI)
332 OS << " def: " << *SVI.DefMI;
395 DepSV.DefMI = SV.DefMI;
484 return SVI->second.DefMI;
602 SVI->second.DefMI = MI;
623 return SVI->second.DefMI;
[all...] |
| RegisterCoalescer.cpp | 170 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
651 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
652 if (!DefMI)
654 const MCInstrDesc &MCID = DefMI->getDesc();
657 // If DefMI is a two-address instruction then commuting it will change the
659 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
662 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
665 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
674 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
707 << *DefMI);
[all...] |
| PeepholeOptimizer.cpp | 294 MachineInstr *DefMI = MRI->getVRegDef(Src);
295 if (!DefMI || !DefMI->getDesc().isBitcast())
299 NumDefs = DefMI->getDesc().getNumDefs();
300 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs;
304 const MachineOperand &MO = DefMI->getOperand(i);
|
| MachineCSE.cpp | 125 MachineInstr *DefMI = MRI->getVRegDef(Reg);
126 if (DefMI->getParent() != MBB)
128 if (!DefMI->isCopy())
130 unsigned SrcReg = DefMI->getOperand(1).getReg();
133 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
137 DEBUG(dbgs() << "Coalescing: " << *DefMI);
141 DefMI->eraseFromParent();
|
| LiveRangeEdit.h | 144 /// values if DefMI may be rematerializable.
145 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
|
| VirtRegRewriter.cpp | 586 MachineInstr *DefMI = I;
588 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
589 MachineOperand &MO = DefMI->getOperand(i);
[all...] |
| ScheduleDAGInstrs.cpp | 599 MachineInstr *DefMI = Def->getInstr();
600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
602 const MachineOperand &MO = DefMI->getOperand(DefIdx);
604 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
625 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
633 unsigned DefClass = DefMI->getDesc().getSchedClass();
|
| MachineSink.cpp | 126 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
127 if (DefMI->isCopyLike())
129 DEBUG(dbgs() << "Coalescing: " << *DefMI);
|
| StrongPHIElimination.cpp | 254 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
255 if (DefMI)
256 PHISrcDefs[DefMI->getParent()].push_back(DefMI);
[all...] |
| TailDuplication.cpp | 226 MachineInstr *DefMI = MRI->getVRegDef(VReg);
228 if (DefMI) {
229 DefBB = DefMI->getParent();
[all...] |
| LiveIntervalAnalysis.cpp | 277 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
278 if (DefMI != 0) {
279 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
[all...] |
| /external/llvm/lib/Target/ |
| TargetInstrInfo.cpp | 66 const MachineInstr *DefMI, unsigned DefIdx,
71 unsigned DefClass = DefMI->getDesc().getSchedClass();
114 const MachineInstr *DefMI,
119 unsigned DefClass = DefMI->getDesc().getSchedClass();
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 620 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
644 const MachineInstr *DefMI, unsigned DefIdx,
673 const MachineInstr *DefMI, unsigned DefIdx,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveIntervalAnalysis.h | 387 MachineInstr *DefMI, SlotIndex InstrIdx,
439 MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
449 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 358 const MachineInstr *DefMI, unsigned DefIdx,
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 455 MachineInstr *DefMI = MRI->getVRegDef(VReg);
457 if (DefMI &&
458 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
[all...] |
