/external/javassist/src/main/javassist/bytecode/ |
Opcode.java | 110 int FSUB = 102; 346 -1, // fsub, 102
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/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 235 FADD, FSUB, FMUL, FMA, FDIV, FREM, [all...] |
/external/qemu/target-i386/ |
ops_sse_header.h | 69 SSE_HELPER_B(psubb, FSUB) 70 SSE_HELPER_W(psubw, FSUB) 71 SSE_HELPER_L(psubl, FSUB) 72 SSE_HELPER_Q(psubq, FSUB)
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ops_sse.h | 334 #define FSUB(a, b) ((a) - (b)) 367 SSE_HELPER_B(helper_psubb, FSUB) 368 SSE_HELPER_W(helper_psubw, FSUB) 369 SSE_HELPER_L(helper_psubl, FSUB) 370 SSE_HELPER_Q(helper_psubq, FSUB) [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB 176 case ISD::FSUB: 460 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { 462 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
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SelectionDAGBuilder.cpp | [all...] |
LegalizeFloatTypes.cpp | 91 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; [all...] |
DAGCombiner.cpp | 389 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 392 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 394 case ISD::FSUB: 398 // fold (fneg (fsub A, B)) -> (fsub B, A) 440 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 442 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 446 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 447 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType() [all...] |
SelectionDAG.cpp | [all...] |
LegalizeDAG.cpp | [all...] |
LegalizeVectorTypes.cpp | 104 case ISD::FSUB: 478 case ISD::FSUB: [all...] |
FastISel.cpp | 888 case Instruction::FSub: 889 // FNeg is currently represented in LLVM IR as a special case of FSub. 892 return SelectBinaryOp(I, ISD::FSUB); [all...] |
/dalvik/dx/src/com/android/dx/cf/code/ |
ByteOps.java | 129 public static final int FSUB = 0x66; 456 "66 - fsub;" +
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BytecodeArray.java | 620 case ByteOps.FSUB: [all...] |
/external/valgrind/main/none/tests/ppc32/ |
round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, 43 "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd", 473 BINOP("fsub"); 932 case FSUB: 1087 case FSUB: 1088 BINOP("fsub");
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/external/valgrind/main/none/tests/ppc64/ |
round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, 43 "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd", 473 BINOP("fsub"); 932 case FSUB: 1087 case FSUB: 1088 BINOP("fsub");
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/prebuilt/common/asm/ |
asm-3.1.jar | |
/external/javassist/src/main/javassist/compiler/ |
CodeGen.java | 935 '-', DSUB, FSUB, LSUB, ISUB, [all...] |
/external/javassist/src/main/javassist/bytecode/analysis/ |
Executor.java | 324 case FSUB: [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | [all...] |
ARMISelLowering.cpp | 461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); [all...] |
/external/llvm/lib/Target/CellSPU/ |
SPUISelDAGToDAG.cpp | 799 // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)) 801 if (Op0.getOpcode() == ISD::FSUB) { [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 690 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); [all...] |
/prebuilt/common/jarjar/ |
jarjar-1.0rc8.jar | |