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    Searched refs:INSERT_SUBREG (Results 1 - 7 of 7) sorted by null

  /external/llvm/include/llvm/Target/
TargetOpcodes.h 43 /// INSERT_SUBREG - This instruction takes three operands: a register that
49 INSERT_SUBREG = 7,
54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
  /external/llvm/lib/CodeGen/
ExpandPostRAPseudos.cpp 112 assert(SubIdx != 0 && "Invalid index for insert_subreg");
229 case TargetOpcode::INSERT_SUBREG:
  /external/llvm/include/llvm/CodeGen/
MachineInstr.h 276 return getOpcode() == TargetOpcode::INSERT_SUBREG;
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 484 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
494 // the INSERT_SUBREG instruction.
496 // %dst = INSERT_SUBREG %src, %sub, SubIdx
507 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
512 // Create the insert_subreg or subreg_to_reg machine instruction.
530 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
663 Opc == TargetOpcode::INSERT_SUBREG ||
    [all...]
ScheduleDAGRRList.cpp     [all...]
SelectionDAG.cpp     [all...]
  /external/llvm/lib/Target/SystemZ/
SystemZISelDAGToDAG.cpp 637 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
718 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,

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